ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 225

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ST7LITE49K2

Manufacturer Part Number
ST7LITE49K2
Description
8-bit MCU
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST7LITE49K2

8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance
10K write/erase cycles guaranteed Data retention
256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention
20 years at 55 °C.
Clock Sources
Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
Five Power Saving Modes
Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

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Figure 122. RESET pin protection when LVD is enabled
1. The reset network protects the device against parasitic resets. The output of the external reset circuit must
2. When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-
3. In case a capacitive power supply is used, it is recommended to connect a 1MΩ pull-down resistor to the
Tips when using the LVD
EXTERNAL
have an open-drain output to drive the ST7 reset pad. Otherwise the device can be damaged when the
ST7 generates an internal reset (LVD or watchdog). Whatever the reset source is (internal or external), the
user must ensure that the level on the RESET pin can go below the V
Section 13.10.1 on page
reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin is less than the absolute maximum value specified for I
Section Table 70. on page
down capacitor is required to filter noise on the reset line.
RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will
add 5µA to the power consumption of the MCU).
RESET
Check that all recommendations related to ICCCLK and reset circuit have been applied
(see caution in
Check that the power supply is properly decoupled (100 nF + 10 µF close to the MCU).
Refer to AN1709 and AN2017. If this cannot be done, it is recommended to put a
100 nF + 1 MΩ pull-down on the RESET pin.
The capacitors connected on the RESET pin and also the power supply are key to
avoid any start-up marginality. In most cases, steps 1 and 2 above are sufficient for a
robust solution. Otherwise: replace 10 nF pull-down on the RESET pin with a 5 µF to
20 µF capacitor.”
Required
0.01μF
Table 2 on page 18
224. Otherwise the reset will not be taken into account internally. Because the
194.
1MΩ
Optional
(note 3)
and notes above).
V
DD
R
ON
Filter
GENERATOR
PULSE
IL
max. level specified in
Electrical characteristics
WATCHDOG
ILLEGAL OPCODE
LVD RESET
INJ(RESET)
INTERNAL
RESET
ST7xxx
225/245
in

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