ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 226

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

Electrical characteristics
13.11
Table 99.
1. Unless otherwise specified, typical data are based on T
2. The maximum ADC clock frequency allowed within V
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than the maximum
4. The stabilization time of the A/D converter is masked by the first t
226/245
Symbol
C
t
R
f
V
t
STAB
ADC
ADC
guidelines and are not tested.
value). Data guaranteed by Design, not tested in production.
valid.
ADC
AIN
AIN
Conversion time (Sample+Hold)
- Sample capacitor loading time
Stabilization time after ADC
Figure 123. RESET pin protection when LVD is disabled
1. The reset network protects the device against parasitic resets.
2. Please refer to
10-bit ADC characteristics
Subject to general operating condition for V
ADC characteristics
Conversion voltage range
Internal sample and hold
ADC clock frequency
- Hold conversion time
External input resistor
The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.
Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin
can go below the V
taken into account internally.
Because the reset circuit is designed to allow the internal Reset to be output in the RESET pin, the user
must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for
I
INJ(RESET)
Required
EXTERNAL
CIRCUIT
RESET
USER
Parameter
capacitor
enable
in
Section Table 70. on page
Section 12.2.1 on page 189
IL
0.01μF
(2)
max. level specified in
2.7 V ≤ V
2.4 V ≤ V
f
V
CPU
V
DD
DD
DD
= 8 MHz, f
A
= 2.4 V to 2.7 V operating range is 1 MHz.
194.
= 3.3 V, f
= 25 °C and V
DD
DD
= 5 V, f
Conditions
for more details on illegal opcode reset conditions.
V
Section 13.10.1 on page
≤5.5 V, f
≤2.7 V, f
DD
R
LOAD
ADC
ON
DD
ADC
ADC
Filter
= 4 MHz
, f
. The first conversion after the enable is then always
= 4 MHz
= 4 MHz
ADC
ADC
DD
OSC
GENERATOR
= 2 MHz
= 1 MHz
-V
SS
, and T
PULSE
= 5 V. They are given only as design
A
224. Otherwise the reset will not be
V
unless otherwise specified.
Min
SSA
Typ
0
3.5
10
6
4
(4)
(1)
WATCHDOG
ILLEGAL OPCODE
10k
20k
V
INTERNAL
RESET
Max
8k
7k
ST7LITE49K2
DDA
4
(3)
(3)
(3)
(3)
ST7XXX
1/f
MHz
Unit
pF
μs
V
Ω
ADC