ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 166

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

On-chip peripherals
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Register description
SPI control register (SPICR)
Reset value: 0000 xxxx (0xh)
Bit 7 = SPIE Serial Peripheral interrupt enable.
Bit 6 = SPE Serial Peripheral output enable.
Bit 5 = SPR2 Divider enable.
Bit 4 = MSTR Master mode.
Bit 3 = CPOL Clock polarity.
SPIE
This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever an End of Transfer event, Master Mode Fault
or Overrun error occurs (SPIF = 1, MODF = 1 or OVR = 1 in the SPICSR register)
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see
reset, so the SPI peripheral is not initially connected to the external pins.
0: I/O pins free for general purpose I/O
1: SPI I/O pin alternate functions enabled
This bit is set and cleared by software and is cleared by reset. It is used with the
SPR[1:0] bits to set the baud rate. Refer to
0: Divider by 2 enabled
1: Divider by 2 disabled
This bit has no effect in slave mode.
This bit is set and cleared by software. It is also cleared by hardware when, in master
mode, SS = 0 (see
0: Slave mode
1: Master mode. The function of the SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are reversed.
This bit is set and cleared by software. This bit determines the idle state of the serial
Clock. The CPOL bit affects both the master and slave modes.
0: SCK pin has a low level idle state
1: SCK pin has a high level idle state
If CPOL is changed at the communication byte boundaries, the SPI must be disabled
by resetting the SPE bit.
7
SPE
Section : Master mode fault
Section : Master mode fault
SPR2
MSTR
Read / Write
Table 52: SPI Master mode SCK
CPOL
(MODF)). The SPE bit is cleared by
(MODF)).
CPHA
SPR1
ST7LITE49K2
Frequency.
SPR0
0