ST7LITE49K2 STMicroelectronics, ST7LITE49K2 Datasheet - Page 149

• Manufacturer Part Number: ST7LITE49K2
• Description: 8-bit MCU
• Manufacturer: STMicroelectronics

Specifications of ST7LITE49K2

• 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 10K write/erase cycles guaranteed Data retention
• 256 Bytes Data Eeprom With Read-out Protection. 300k Write/erase Cycles Guaranteed, Data Retention: 20 years at 55 °C.
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto-wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-halt, Auto-wakeup from Halt, Wait and Slow

ST7LITE49K2
Bit 1 = STOP Generation of a Stop condition bit
●
●
Bit 0 = ITE Interrupt Enable bit
This bit is set and cleared by software. It is also cleared by hardware in master mode.
Note: This bit is not cleared when the interface is disabled (PE=0).
In master mode:
0: No stop generation
1: Stop generation after the current byte transfer or after the current Start condition is
sent. The STOP bit is cleared by hardware when the Stop condition is sent.
In slave mode:
0: No stop generation
1: Release the SCL and SDA lines after the current byte transfer (BTF=1). In this mode
the STOP bit has to be cleared by software.
This bit is set and cleared by software and cleared by hardware when the interface is
disabled (PE=0).
0: Interrupts disabled
1: Interrupts enabled
Refer to
SCL is held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (See
Figure
71) is detected.
Figure 72
for the relationship between the events and the interrupt.
On-chip peripherals
149/245