STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 97

• Manufacturer Part Number: STM32W108CZ
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CZ

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
9.8.4
Table 55.
9.9
9.9.1
Table 56.
31
15
31
15
30
14
30
14
Bits [7:0]
Serial controller interrupt mode register (SCx_INTMODE)
Address offset: 0xA854 (SC1_INTMODE) and 0xA858 (SC2_INTMODE)
Reset value:
Serial controller interrupt mode register (SCx_INTMODE)
SPI master mode registers
Serial data register (SCx_DATA)
Address offset: 0xC83C (SC1_DATA) and 0xC03C (SC2_DATA)
Reset value:
Serial data register (SCx_DATA)
Bit 2
Bit 1
Bit 0
29
13
29
13
SC_TXIDLELEVEL: Transmitter idle interrupt mode
0: Edge triggered
SC_TXFREELEVEL: Transmit buffer free interrupt mode
0: Edge triggered
SC_RXVALLEVEL: Receive buffer has data interrupt mode
0: Edge triggered
SC_DATA: Transmit and receive data register. Writing to this register adds a byte to the transmit
FIFO. Reading from this register takes the next byte from the receive FIFO and clears the
overrun error bit if it was set.
In UART mode (SC1 only), reading from this register loads the UART status register with the
parity and frame error status of the next byte in the FIFO, and clears these bits if the FIFO is
now empty.
28
12
28
12
Reserved
27
11
27
11
0x0000 0000
0x0000 0000
26
10
26
10
Reserved
25
25
9
9
Doc ID 16252 Rev 13
24
24
8
8
Reserved
Reserved
23
23
7
7
22
22
6
6
1: Level triggered.
1: Level triggered.
1: Level triggered.
21
21
5
5
20
20
4
4
SC_DATA
rw
19
19
3
3
SC_TX
IDLEL
EVEL
Serial interfaces
18
18
rw
2
2
SC_TX
FREEL
EVEL
17
17
rw
1
1
97/232
SC_RX
VALLE
VEL
16
rw
16
0
0