STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 44
STM32W108CZ
Manufacturer Part Number
STM32W108CZ
Description
High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
Manufacturer
STMicroelectronics
Datasheet
1.STM32W108CC.pdf
(232 pages)
Specifications of STM32W108CZ
Receive Current (w/ Cpu)
27 mA
Transmit Current (w/ Cpu, +3 Dbm Tx)
31 mA
Low Deep Sleep Current, With Retained Ram And Gpio
400 nA/800 nA with/without sleep timer
Standard Arm Debug Capabilities
Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
Single Voltage Operation
2.1-3.6 V with internal 1.8 V and 1.25 V regulators
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System modules
Table 8.
6.4
6.4.1
44/232
31
15
30
14
CPU clock source select register (CPU_CLK_SEL)
Address offset: 0x4000 4020
Reset value: 0x0000 0000
CPU clock source select register (CPU_CLK_SEL)
System timers
Watchdog timer
The STM32W108 integrates a watchdog timer which can be enabled to provide protection
against software crashes and ARM® Cortex-M3 CPU lockup. By default, it is disabled at
power up of the always-on power domain. The watchdog timer uses the calibrated 1 kHz
clock (CLK1K) as its reference and provides a nominal 2.048 s timeout. A low water mark
interrupt occurs at 1.792 s and triggers an NMI to the ARM® Cortex-M3 NVIC as an early
warning. When enabled, periodically reset the watchdog timer by writing to the
WDOG_RESTART register before it expires.
The watchdog timer can be paused when the debugger halts the ARM® Cortex-M3. To
enable this functionality, set the bit DBG_PAUSE in the SLEEP_CONFIG register.
If the low-frequency internal RC oscillator (OSCRC) is turned off during deep sleep, CLK1K
stops. As a consequence the watchdog timer stops counting and is effectively paused
during deep sleep.
The watchdog enable/disable bits are protected from accidental change by requiring a two
step process. To enable the watchdog timer the application must first write the enable code
0xEABE to the WDOG_CTRL register and then set the WDOG_EN register bit. To disable
the timer the application must write the disable code 0xDEAD to the WDOG_CTRL register
and then set the WDOG_DIS register bit.
Bit 0
29
13
CPU_CLK_SEL: When set to ‘0’, 12-MHz CPU clock is selected. When set to ‘1’, 24-MHz CPU
clock is selected. Note that the clock selection also determines if RAM controller is running at
the same speed as the HCLK (CPU_CLK_SEL = ‘1’) or double speed of HCLK (CPU_CLK_SEL
= ‘0’).
28
12
27
11
26
10
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
25
9
Doc ID 16252 Rev 13
Rserved
24
8
Reserved
23
7
22
6
21
5
20
4
19
3
18
2
17
1
LK_SEL
CPU_C
rws
16
0
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