STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 39
STM32W108CZ
Manufacturer Part Number
STM32W108CZ
Description
High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
Manufacturer
STMicroelectronics
Datasheet
1.STM32W108CC.pdf
(232 pages)
Specifications of STM32W108CZ
Receive Current (w/ Cpu)
27 mA
Transmit Current (w/ Cpu, +3 Dbm Tx)
31 mA
Low Deep Sleep Current, With Retained Ram And Gpio
400 nA/800 nA with/without sleep timer
Standard Arm Debug Capabilities
Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
Single Voltage Operation
2.1-3.6 V with internal 1.8 V and 1.25 V regulators
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STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
6.2.3
Reset generation
The Reset Generation module responds to reset sources and generates the following reset
signals:
●
●
●
●
●
Table 4
Table 4.
POR HV
POR LV (in deep sleep)
POR LV (not in deep
sleep)
RSTB
Watchdog reset
Software reset
Option byte error
Normal deep sleep
Emulated deep sleep
Debug reset
PORESET
SYSRESET
DAPRESET
PRESETHV
PRESETLV
Reset source
shows which reset sources generate certain resets.
Generated resets
PORESET
Reset of the ARM® Cortex-M3 CPU and ARM® Cortex-M3
System Debug components (Flash Patch and Breakpoint,
Data Watchpoint and Trace, Instrumentation Trace Macrocell,
Nested Vectored Interrupt Controller). ARM defines
PORESET as the region that is reset when power is applied.
Reset of the ARM® Cortex-M3 CPU without resetting the
Core Debug and System Debug components, so that a live
system can be reset without disturbing the debug
configuration.
Reset to the SWJ's AHB Access Port (AHB-AP).
Peripheral reset for always-on power domain, for peripherals
that are required to retain their configuration across a deep
sleep cycle.
Peripheral reset for core power domain, for peripherals that
are not required to retain their configuration across a deep
sleep cycle.
Doc ID 16252 Rev 13
X
X
X
X
X
X
SYSRESET
X
X
X
X
X
X
X
X
X
X
Reset generation
DAPRESET
X
X
X
X
PRESETHV
X
X
X
X
X
System modules
PRESETLV
X
X
X
X
X
X
X
X
X
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