STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 47

• Manufacturer Part Number: STM32W108CZ
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CZ

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Table 11.
Table 12.
31
15
31
15
Reserved
30
14
30
14
Bits [15:0]
r
Bits [7:4]
Bit 12
Bit 11
Bit 10
Sleep timer configuration register (SLEEPTMR_CFG)
Sleep timer count high register (SLEEPTMR_CNTH)
Address:
Reset value:
Sleep timer count high register (SLEEPTMR_CNTH)
Bit 0
29
13
29
13
SLEEPTMR_REVERSE:
SLEEPTMR_ENABLE:
SLEEPTMR_DBGPAUSE: Debug Pause
SLEEPTMR_CLKDIV: Sleep timer prescaler setting
SLEEPTMR_CLKSEL: Clock Select
SLEEPTMR_CNTH_FIELD:
SLEEP
TMR_
REVER
SE
0: count forward; 1: count backwards.
Only changes when ENABLE bit is set to ‘0’.
0: disable sleep timer; 1: enable sleep timer.
To change other register bits (REVERSE, CLK_DIV, CLK_SEL), this bit must be set to ‘0’.
Enabling/Disabling latency can be up 2 to 3 clock-periods of selected clock.
0: The timer continues working in Debug mode.
1: The timer is paused in Debug mode when the CPU is halted.
Divides clock by 2
Can only be changed when the ENABLE bit is set to ‘0’.
0: Calibrated 1kHz RC clock (default); 1: 32kHz
Can only be changed when the ENABLE bit is set to ‘0’.
Sleep timer counter high value [31:16].
Reading this register updates the SLEEP_COUNT_L for subsequent reads.
28
12
28
12
rw
SLEEP
ENABL
TMR_
27
11
27
11
rw
E
0x4000 6010
0x0000 0000
DBGPA
26
10
SLEEP
TMR_
USE
26
10
rw
N
where N = 0 to 15.
25
9
Doc ID 16252 Rev 13
25
9
Reserved
SLEEPTMR_CNTH
r
24
8
Reserved
Reserved
24
8
r
23
7
23
7
SLEEPTMR_CLKDIV
22
6
22
6
rw
21
5
21
5
20
4
20
4
19
3
19
3
System modules
Reserved
18
2
18
r
2
17
1
17
1
47/232
MR_
SLE
EPT
CLK
SEL
16
16
0
rw
0