ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 84

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

ADuC7124/ADuC7126
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 25 interrupt sources on the ADuC7124/ADuC7126
that are controlled by the interrupt controller. All interrupts
are generated from the on-chip peripherals, except for the
software interrupt (SWI), which is programmable by the user.
The ARM7TDMI CPU core recognizes interrupts as one of
two types: a normal interrupt request (IRQ) and a fast interrupt
request (FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through a number of interrupt-related registers. The
bits in each IRQ and FIQ register represent the same interrupt
source as described in Table 126.
The ADuC7124/ADuC7126 contain a vectored interrupt control-
ler (VIC) that supports nested interrupts up to eight levels. The
VIC also allows the programmer to assign priority levels to all
interrupt sources. Interrupt nesting must be enabled by setting
the ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full-vectored interrupt controller is
enabled.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
Table 126. IRQ/FIQ MMRs Bit Descriptions
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Description
All interrupts OR’ed
(FIQ only)
Software interrupt
Timer0
Timer1
Timer2 or wake-up
timer
Timer3 or watchdog
timer
Flash Control 0
Flash Control 1
ADC
UART0
UART1
PLL lock
I2C0 master IRQ
I2C0 slave IRQ
I2C1 master IRQ
I2C1 slave IRQ
SPI
XIRQ0 (GPIO IRQ0 )
Comparator
PSM
XIRQ1 (GPIO IRQ1)
Comments
This bit is set if any FIQ is active.
User programmable interrupt
source.
General-Purpose Timer 0.
General-Purpose Timer 1.
General-Purpose Timer 2 or
wake-up timer.
General-Purpose Timer 3 or
watchdog timer.
Flash controller for Block 0
interrupt.
Flash controller for Block 1
interrupt.
ADC interrupt source bit.
UART0 interrupt source bit.
UART1 interrupt source bit.
PLL lock bit.
I
I
I
I
SPI interrupt source bit.
External Interrupt 0.
Voltage comparator source bit.
Power supply monitor.
External Interrupt 1.
2
2
2
2
C master interrupt source bit.
C slave interrupt source bit.
C master interrupt source bit.
C slave interrupt source bit.
Rev. B | Page 84 of 104
Bit
21
22
23
24
25
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It services general-purpose interrupt handling of
internal and external events.
All 32 bits are logically OR’ e d to create a single IRQ signal to the
ARM7TDMI core. Descriptions of the four 32-bit registers
dedicated to IRQ follow.
IRQSTA Register
IRQSTA is a read-only register that provides the current-enabled
IRQ source status (effectively a logic AND of the IRQSIG and
IRQEN bits). When set to 1, that source generates an active IRQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
IRQSTA Register
Name:
Address:
Default Value:
Access:
IRQSIG Register
IRQSIG reflects the status of the various IRQ sources. If a periph-
eral generates an IRQ signal, the corresponding bit in the
IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is
read only. This register should not be used in an interrupt
service routine for determining the source of an IRQ exception;
IRQSTA should only be used for this purpose.
IRQSIG Register
Name:
Address:
Default Value:
Access:
Description
PLA IRQ0
XIRQ2 (GPIO IRQ2 )
XIRQ3 (GPIO IRQ3)
PLA IRQ1
PWM
IRQSIG
0xFFFF0004
0x00000000
Read only
IRQSTA
0xFFFF0000
0x00000000
Read only
Comments
PLA Block 0 IRQ bit.
External Interrupt 2.
External Interrupt 3.
PLA Block 1 IRQ bit.
PWM trip interrupt source bit.