ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 48

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

ADuC7124/ADuC7126
Table 56. FEE0PRO and FEE0HID MMR Bit Descriptions
Bit
31
[30:0]
Table 57. FEE1PRO and FEE1HID MMR Bit Descriptions
Bit
31
30
[29:0]
EXECUTION TIME FROM SRAM AND FLASH/EE
This section describes SRAM and Flash/EE access times during
execution for applications where execution time is critical.
Execution from SRAM
Fetching instructions from SRAM takes one clock cycle because
the access time of the SRAM is 2 ns, and a clock cycle is 24 ns
minimum. However, if the instruction involves reading or
writing data to memory, one extra cycle must be added if the
data is in SRAM (or three cycles if the data is in Flash/EE): one
cycle to execute the instruction and two cycles to get the 32-bit
data from Flash/EE. A control flow instruction (a branch
instruction, for example) takes one cycle to fetch but also takes
two cycles to fill the pipeline with the new instructions.
Execution from Flash/EE
Because the Flash/EE width is 16 bits and access time for 16-bit
words is 22 ns, execution from Flash/EE cannot be done in
one cycle (as can be done from SRAM when the CD bit = 0).
Also, some dead times are needed before accessing data for any
value of the CD bits.
In ARM mode, where instructions are 32 bits, two cycles are
needed to fetch any instruction when CD = 0. In Thumb mode,
where instructions are 16 bits, one cycle is needed to fetch any
instruction.
Description
Read protection.
Cleared by the user to protect Block 0.
Set by the user to allow reading of Block 0.
Write protection for Page 123 to Page 120, for Page 119
to Page 116, and for Page 0 to Page 3.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing to the pages.
Description
Read protection.
Cleared by the user to protect Block 1.
Set by the user to allow reading of Block 1.
Write protection for Page 127 to Page 120.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing to the pages.
Write protection for Page 119 to Page 116 and for Page 0
to Page 3.
Cleared by the user to protect the pages in writing.
Set by the user to allow writing to the pages.
Rev. B | Page 48 of 104
Timing is identical in both modes when executing instructions
that involve using the Flash/EE for data memory. If the instruc-
tion to be executed is a control flow instruction, an extra cycle
is needed to decode the new address of the program counter,
and then four cycles are needed to fill the pipeline. A data pro-
cessing instruction involving only the core register does not
require any extra clock cycles. However, if it involves data in
Flash/EE, an extra clock cycle is needed to decode the address
of the data, and two cycles are needed to get the 32-bit data from
Flash/EE. An extra cycle must also be added before fetching
another instruction. Data transfer instructions are more complex
and are summarized in Table 58.
Table 58. Execution Cycles in ARM/Thumb Mode
Instructions
LD
LDH
LDM/PUSH
STR
STRH
STRM/POP
1
2
RESET AND REMAP
The ARM exception vectors are all situated at the bottom of the
memory array, from Address 0x00000000 to Address 0x00000020,
as shown in Figure 40.
By default, and after any reset, the Flash/EE is mirrored at the
bottom of the memory array. The remap function allows the
programmer to mirror the SRAM at the bottom of the memory
array, which facilitates execution of exception routines from
SRAM instead of from Flash/EE. This means exceptions are
executed twice as fast, being executed in 32-bit ARM mode with
32-bit wide SRAM instead of 16-bit wide Flash/EE memory.
KERNEL
INTERRUPT
SERVICE ROUTINES
INTERRUPT
SERVICE ROUTINES
ARM EXCEPTION
VECTOR ADDRESSES
The SWAP instruction combines an LD and STR instruction with only one
N is the number of data bytes to load or store in the multiple load/store
fetch, giving a total of eight cycles + 40 ns.
instruction (1 < N ≤ 16).
1
1
Figure 40. Remap for Exception Execution
Fetch
Cycles
2/1
2/1
2/1
2/1
2/1
2/1
0x00000020
0x00000000 0x00000000
Dead
Time
1
1
N
1
1
N
2
1
0x00080000
0x00040000
Data Access
2
1
2 × N
2 × 20 ns
20 ns
2 × N × 20 ns
0xFFFFFFFF
0x00047FFF
0x0009F800
2
FLASH/EE
SRAM
MIRROR SPACE
1
Dead
Time
1
1
N
1
1
N
1
1