ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 54

• Manufacturer Part Number: ADUC7126
• Description: Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
• Manufacturer: Analog Devices

Specifications of ADUC7126

• Mcu Core: ARM7 TDMI
• Mcu Speed (mips): 40
• Gpio Pins: 40
• Adc # Channels: 16
• Other: PWM

ADuC7124/ADuC7126
Comparator Interface
The comparator interface consists of a 16-bit MMR, CMPCON,
which is described in Table 69.
CMPCON Register
Name:
Address:
Default Value:
Access:
Table 69. CMPCON MMR Bit Descriptions
Bit
[15:11]
10
[9:8]
[7:6]
5
[4:3]
2
Value
00
01
10
11
00
01
10
11
00
11
01/10
Name
CMPEN
CMPIN
CMPOC
CMPOL
CMPRES
CMPHYST
Description
Reserved.
Comparator enable bit.
Set by the user to enable the
comparator.
Cleared by the user to disable the
comparator.
Comparator negative input select
bits.
AV
ADC3 input.
DAC0 output.
Reserved.
Comparator output configuration
bits.
Reserved.
Reserved.
Output on CMP
IRQ.
Comparator output logic state bit.
When low, the comparator output
is high if the positive input
(CMP0) is above the negative
input (CMP1). When high, the
comparator output is high if the
positive input is below the
negative input.
Response time.
5 µs response time typical for
large signals (2.5 V differential).
17 µs response time typical for
small signals (0.65 mV
differential).
4 µs typical.
Reserved.
Comparator hysteresis sit.
Set by user to have a hysteresis of
about 7.5 mV.
Cleared by user to have no
hysteresis.
DD
CMPCON
0xFFFF0444
0x0000
Read/write
/2.
OUT
.
Rev. B | Page 54 of 104
Bit
1
0
OSCILLATOR AND PLL—POWER CONTROL
Clocking System
The ADuC7124/ADuC7126 integrate a 32.768 kHz ± 3% oscilla-
tor, a clock divider, and a PLL. The PLL locks onto a multiple
(1275) of the internal oscillator or an external 32.768 kHz crystal to
provide a stable 41.78 MHz clock (UCLK) for the system. To allow
power saving, the core can operate at this frequency or at binary
submultiples of it. The actual core operating frequency, UCLK/2
is referred to as HCLK. The default core clock is the PLL clock
divided by 8 (CD = 3) or 5.22 MHz. The core clock frequency
can also come from an external clock on the ECLK pin as
shown in Figure 45. The core clock can be output on ECLK
when using an internal oscillator or external crystal.
Note that, when the ECLK pin is used to output the core clock,
the output signal is not buffered and is not suitable for use as a
clock source to an external device without an external buffer.
The selection of the clock source is in the PLLCON register. By
default, the part uses the internal oscillator feeding the PLL.
WATCHDOG
*32.768kHz ±3%
WAKEUP
TIMER
TIMER
Value
CORE
Name
CMPORI
CMPOFI
OSCILLATOR
INT. 32kHz*
Figure 45. Clocking System
PLL
I
2
C
32.768kHz
CD
41.78MHz
Description
Comparator output rising edge
interrupt.
Set automatically when a rising
edge occurs on the monitored
voltage (CMP0).
Cleared by user by writing a 1 to
this bit.
Comparator output falling edge
interrupt.
Set automatically when a falling
edge occurs on the monitored
voltage (CMP0).
Cleared by user.
UCLK
AT POWER UP
OSCILLATOR
CRYSTAL
ECLK
/2
OCLK
CD
HCLK
PERIPHERALS
MDCLK
ANALOG
XCLKO
XCLKI
XCLK
CD
,