ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 96

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ADUC7126

Manufacturer Part Number
ADUC7126
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7126

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Gpio Pins
40
Adc # Channels
16
Other
PWM

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ADuC7124/ADuC7126
T3CLRI Register
Name:
Address:
Default Value:
Access:
T3CLRI is an 8-bit register. Writing any value to this register on
successive occassions clears the Timer3 interrupt in normal
mode or resets a new timeout period in watchdog mode.
Note that the user must perform successive writes to this
register to ensure resetting the timeout period.
Secure Clear Bit (Watchdog Mode Only)
The secure clear bit is provided for a higher level of protection.
When set, a specific sequential value must be written to T3CLRI
to avoid a watchdog reset. The value is a sequence generated
by the 8-bit linear feedback shift register (LFSR) polynomial =
X
CLOCK
The initial value or seed is written to T3CLRI before entering
watchdog mode. After entering watchdog mode, a write to
T3CLRI must match this expected value. If it matches, the LFSR
is advanced to the next state when the counter reload occurs. If
it fails to match the expected state, a reset is immediately
generated, even if the count has not yet expired.
The value 0x00 should not be used as an initial seed due to the
properties of the polynomial. The value 0x00 is always guaran-
teed to force an immediate reset. The value of the LFSR cannot
be read; it must be tracked/generated in software.
Example of a sequence:
1.
2.
3.
4.
5.
EXTERNAL MEMORY INTERFACING
The ADuC7124/ADuC7126 feature an external memory
interface. The external memory interface requires a larger
number of pins. The XMCFG MMR must be set to 1 to use the
external port.
Although 32-bit addresses are supported internally, only the
lower 16 bits of the address are on external pins.
The memory interface can address up to four 128 kB of
asynchronous memory (SRAM or/and EEPROM).
8
+ X
Q
Enter initial seed, 0xAA, in T3CLRI before starting Timer3
in watchdog mode.
Enter 0xAA in T3CLRI; Timer3 is reloaded.
Enter 0x37 in T3CLRI; Timer3 is reloaded.
Enter 0x6E in T3CLRI; Timer3 is reloaded.
Enter 0x66. 0xDC was expected; the watchdog resets the chip.
7
6
D
+ X
Q
6
5
D
+ X + 1, as shown in Figure 56.
T3CLRI
0xFFFF036C
0x00
Write only
Q
5
D
Figure 56. 8-Bit LFSR
Q
4
D
Q
3
D
Q
2
D
Q
1
D
Q
0
D
Rev. B | Page 96 of 104
The pins required for interfacing to an external memory are
shown in Table 145.
Table 145. External Memory Interfacing Pins
Pin
AD[15:0]
A16
MS[3:0]
WS
RS
AE
BHE,
There are four external memory regions available as described
in Table 146. Associated with each region are the MS[3:0] pins.
These signals allow access to the particular region of external
memory. The size of each memory region can be 128 kB maxi-
mum, 64 k × 16 or 128 kB × 8. To access 128 kB with an 8-bit
memory, an extra address line (A16) is provided (see the example
in Figure 57). The four regions are configured independently.
Table 146. Memory Regions
Address Start
0x10000000
0x20000000
0x30000000
0x40000000
Each external memory region can be controlled through three
MMRs: XMCFG, XMxCON, and XMxPAR.
BLE
ADuC7126
AD15:AD0
Figure 57. Interfacing to External EEPROM/RAM
Function
Address/data bus.
Extended addressing for 8-Bit memory only.
Memory select.
Write strobe.
Read strobe.
Address latch enable.
Byte write capability.
MS0
MS1
A16
WS
AE
RS
Address End
0x1000FFFF
0x2000FFFF
0x3000FFFF
0x4000FFFF
LATCH
Contents
External Memory 0
External Memory 1
External Memory 2
External Memory 3
D0:D15
A0:A15
CS
WE
OE
D0:D7
A16
A0:A15
CS
WE
OE
64k × 16-BIT
128k × 8-BIT
EEPROM
RAM

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