ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 74

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ADUC7126

Manufacturer Part Number
ADUC7126
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7126

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Gpio Pins
40
Adc # Channels
16
Other
PWM

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ADuC7124/ADuC7126
I
Name:
Address:
Default Value:
Access:
Function:
Table 107. I2CxADR1 MMR in 10-Bit Address Mode
Bit
[7:0]
I
Name:
Address:
Default Value:
Access:
Function:
Table 109. I2CxSCON MMR Bit Descriptions
Bit
[15:11]
10
9
8
7
6
2
2
C Address 1 Register
C Master Clock Control Register
Name
I2CLADR
Name
I2CSTXENI
I2CSRXENI
I2CSSENI
I2CNACKEN
I2CSSEN
I2C0ADR1, I2C1ADR1
0xFFFF081C, 0xFFFF091C
0x00
Read/write
This 8-bit MMR is used in 10-bit addressing
mode only. This register contains the least
significant byte of the address.
I2C0DIV, I2C1DIV
0xFFFF0824, 0xFFFF0924
0x1F1F
Read/write
This MMR controls the frequency of the I
clock generated by the master on to the SCL
pin. For further details, see the I
Description
These bits contain ADDR[7:0] in 10-bit
addressing mode.
Description
Reserved.
Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
I
Set this bit to enable an interrupt on detecting a stop condition on the I
Clear this interrupt source.
I
Set this bit to NACK the next byte in the transmission sequence.
Clear this bit to let the hardware control the ACK/NACK sequence.
I
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low
until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling
edge.
Clear this bit to disable clock stretching.
2
2
2
C stop condition detected interrupt enable bit.
C NACK enable bit.
C slave SCL stretch enable bit.
2
C section.
2
C
Rev. B | Page 74 of 104
Table 108. I2CxDIV MMR
Bit
[15:8]
[7:0]
I
I
Name:
Address:
Default Value:
Access:
Function:
2
2
C Slave Registers
C Slave Control Register
Name
DIVH
DIVL
I2C0SCON, I2C1SCON
0xFFFF0828, 0xFFFF0928
0x0000
Read/write
This 16-bit MMR configures the I
peripheral in slave mode.
Description
These bits control the duration of the high
period of SCL.
These bits control the duration of the low
period of SCL.
2
C bus.
2
C

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