ADUC7126 Analog Devices, ADUC7126 Datasheet - Page 100

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ADUC7126

Manufacturer Part Number
ADUC7126
Description
Precision Analog Microcontroller, 12-Bit Analog I/O, Large Memory, ARM7TDMI MCU with Enhanced IRQ Handler
Manufacturer
Analog Devices
Datasheet

Specifications of ADUC7126

Mcu Core
ARM7 TDMI
Mcu Speed (mips)
40
Gpio Pins
40
Adc # Channels
16
Other
PWM

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ADuC7124/ADuC7126
HARDWARE DESIGN CONSIDERATIONS
POWER SUPPLIES
The ADuC7124/ADuC7126 operational power supply voltage
range is 2.7 V to 3.6 V. Separate analog and digital power supply
pins (AV
relatively free of noisy digital signals often present on the
system IOV
split supplies; that is, it can use different voltage levels for each
supply. For example, the system can be designed to operate
with an IOV
at 3 V or vice versa. A typical split supply configuration is
shown in Figure 62.
As an alternative to providing two separate power supplies, the
user can reduce noise on AV
and/or ferrite bead between AV
AV
shown in Figure 63. With this configuration, other analog circuitry
(such as op amps, voltage reference, or any other analog circuitry)
can be powered from the AV
Notice that in both Figure 62 and Figure 63, a large value (10 µF)
reservoir capacitor sits on IOV
sits on AV
located at each AV
design practice, be sure to include all of these capacitors and ensure
that the smaller capacitors are close to each AV
lengths as short as possible. Connect the ground terminal of
each of these capacitors directly to the underlying ground plane.
DD
DIGITAL SUPPLY
+
DIGITAL
SUPPLY
+
separately to ground. An example of this configuration is
0.1µF
0.1µF
DD
DD
and IOV
DD
. In addition, local small-value (0.1 µF) capacitors are
DD
Figure 63. External Single Supply Connections
10µF
10µF
Figure 62. External Dual Supply Connections
line. In this mode, the part can also operate with
voltage level of 3.3 V while the AV
DD
IOV
IOGND
DD
ADuC7124/
and IOV
ADuC7126
DD
, respectively) allow AV
IOV
IOV
IOV
DGND
DGND
DGND
ADuC7124/
ADuC7126
DD
DD
DD
DACGND
DACV
GND
DD
DD
AGND
BEAD
AV
DD
DD
DD
REF
supply line as well.
by placing a small series resistor
DD
DD
pin of the chip. As per standard
and IOV
, and a separate 10 µF capacitor
AGND
AV
DD
DD
and then decoupling
10µF
10µF
DD
ANALOG SUPPLY
DD
ANALOG
SUPPLY
to be kept
pin with trace
DD
0.1µF
0.1µF
level can be
+
Rev. B | Page 100 of 104
Finally, note that the analog and digital ground pins on the
ADuC7124/ADuC7126 must be referenced to the same system
ground reference point at all times.
IOV
The IOV
is the supply source for the internal oscillator and PLL circuits.
When the internal PLL loses lock, the clock source is removed
by a gating circuit from the CPU, and the ARM7TDMI core
stops executing code until the PLL regains lock. This feature
ensures that no flash interface timings or ARM7TDMI timings
are violated.
Typically, frequency noise greater than 50 kHz and 50 mV p-p
on top of the supply causes the core to stop working.
If decoupling values recommended in the Power Supplies
section do not sufficiently dampen all noise sources below
50 mV on IOV
recommended.
Linear Voltage Regulator
The ADuC7124/ADuC7126 require a single 3.3 V supply, but
the core logic requires a 2.6 V supply. An on-chip linear
regulator generates the 2.6 V from IOV
LV
compensation capacitor of 0.47 µF must be connected between
LV
tank of charge as shown in Figure 65.
The LV
recommended to use excellent power supply decoupling on
IOV
chip voltage regulator.
DD
DD
DD
DD
pin is the 2.6 V supply for the core logic. An external
and DGND (as close as possible to these pins) to act as a
DIGITAL
SUPPLY
Supply Sensitivity
to help improve line regulation performance of the on-
DD
DD
pin should not be used for any other chip. It is also
supply is sensitive to high frequency noise because it
Figure 64. Recommended IOV
+
Figure 65. Voltage Regulator Connections
DD
0.47µF
1µH
, a filter such as the one shown in Figure 64 is
0.1µF
10µF
0.1µF
LV
DGND
ADuC7124/
ADuC7126
DD
IOV
IOGND
DD
DD
ADuC7124/
ADuC7126
Supply Filter
DD
for the core logic. The

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