SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 774
SAM3A4C
Manufacturer Part Number
SAM3A4C
Description
Manufacturer
Atmel Corporation
- Current page: 774 of 1465
- Download datasheet (26Mb)
774
774
SAM3X/A
SAM3X/A
• Test Modes
• Supports Connection of Two Peripheral DMA Controller Channels (PDC)
– Master or Slave
– Processing of frames with up to 256 data bytes
– Response Data length can be configurable or defined automatically by the Identifier
– Self synchronization in Slave node configuration
– Automatic processing and verification of the “Synch Break” and the “Synch Field”
– The “Synch Break” is detected even if it is partially superimposed with a data byte
– Automatic Identifier parity calculation/sending and verification
– Parity sending and verification can be disabled
– Automatic Checksum calculation/sending and verification
– Checksum sending and verification can be disabled
– Support both “Classic” and “Enhanced” checksum types
– Full LIN error checking and reporting
– Frame Slot Mode: the Master allocates slots to the scheduled frames automatically.
– Generation of the Wakeup signal
– Remote Loopback, Local Loopback, Automatic Echo
– Offers Buffer Transfer without Processor Intervention
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
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