SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 1060
SAM3A4C
Manufacturer Part Number
SAM3A4C
Description
Manufacturer
Atmel Corporation
- Current page: 1060 of 1465
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38.7.40
Name:
Address:
Access:
This register can only be written if the bits WPSWS3 and WPHWS3 are cleared in
page
Only the first 16 bits (channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the channel counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the channel counter source clock and can
be calculated:
1060
1060
1051.
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
– By using the PWM master clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32,
– By using the PWM master clock (MCK) divided by one of both DIVA or DIVB divider, the formula becomes,
31
23
15
–
7
64, 128, 256, 512, or 1024). The resulting period formula will be:
respectively:
64, 128, 256, 512, or 1024). The resulting period formula will be:
------------------------------------------ -
respectively:
----------------------------------------------------- -
------------------------------- -
------------------------------------------ -
2
2
X
CRPD
SAM3X/A
SAM3X/A
PWM Channel Period Register
MCK
X
CPRD
CPRD
MCK
MCK
PWM_CPRDx [x=0..7]
0x4009420C [0], 0x4009422C [1], 0x4009424C [2], 0x4009426C [3], 0x4009428C [4], 0x400942AC [5],
0x400942CC [6], 0x400942EC [7]
Read-write
MCK
CPRD
DIVA
DIVA
30
22
14
–
6
or
or
------------------------------------------ -
CRPD
----------------------------------------------------- -
2
MCK
CPRD
DIVB
MCK
29
21
13
–
5
DIVB
28
20
12
–
4
CPRD
CPRD
CPRD
27
19
11
–
3
“PWM Write Protect Status Register” on
26
18
10
–
2
25
17
–
9
1
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
24
16
–
8
0
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