SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 169
SAM3A4C
Manufacturer Part Number
SAM3A4C
Description
Manufacturer
Atmel Corporation
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• PENDSTSET
RW
SysTick exception set-pending bit.
Write:
0: no effect
1: changes SysTick exception state to pending.
Read:
0: SysTick exception is not pending
1: SysTick exception is pending.
• PENDSTCLR
WO
SysTick exception clear-pending bit.
Write:
0: no effect
1: removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is Unknown.
• Reserved for Debug use
RO
This bit is reserved for Debug use and reads-as-zero when the processor is not in Debug.
• ISRPENDING
RO
Interrupt pending flag, excluding Faults:
0: interrupt not pending
1: interrupt pending.
• VECTPENDING
RO
Indicates the exception number of the highest priority pending enabled exception:
0: no pending exceptions
Nonzero = the exception number of the highest priority pending enabled exception.
The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
SAM3X/A
SAM3X/A
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