SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 727
SAM3A4C
Manufacturer Part Number
SAM3A4C
Description
Manufacturer
Atmel Corporation
- Current page: 727 of 1465
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11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
Figure 33-20. TWI Read Operation with Multiple Data Bytes with or without Internal Address
No
Read Receive Holding register (TWI_RHR)
Read Receive Holding register (TWI_RHR)
(CLDIV, CHDIV, CKDIV) in TWI_CWGR
- Internal address size (if IADR used)
Set the Master Mode register:
TWI_CR = MSEN + SVDIS
Read ==> bit MREAD = 1
Internal address size = 0?
Set the Control register:
- Device slave address
- Transfer direction bit
Read Status register
Read Status register
Read status register
(Needed only once)
TWI_CR = START
TWI_CR = STOP
Yes
Start the transfer
Last data to read
Stop the transfer
- Master enable
TXCOMP = 1?
Set TWI clock
RXRDY = 1?
Yes
Yes
Yes
RXRDY = 1?
Yes
but one?
BEGIN
END
No
No
No
Set the internal address
TWI_IADR = address
SAM3X/A
SAM3X/A
727
727
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