SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 1126

• Manufacturer Part Number: SAM3A4C
• Manufacturer: Atmel Corporation

This bit is cleared when WAKEUPEC bit in UOTGHS_DEVIDR is written to one.
• EORSTE: End of Reset Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when EORSTES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when EORSTEC bit in UOTGHS_DEVIDR is written to one.
• SOFE: Start of Frame Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when SOFES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when SOFEC bit in UOTGHS_DEVIDR is written to one.
• MSOFE: Micro Start of Frame Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when MSOFES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when MSOFEC bit in UOTGHS_DEVIDR is written to one.
• SUSPE: Suspend Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when SUSPES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when SUSPEC bit in UOTGHS_DEVIDR is written to one.
1126
1126
SAM3X/A
SAM3X/A
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12