SAM3A4C Atmel Corporation, SAM3A4C Datasheet - Page 405
SAM3A4C
Manufacturer Part Number
SAM3A4C
Description
Manufacturer
Atmel Corporation
- Current page: 405 of 1465
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25.4
25.4.1
25.4.1.1
Table 25-2.
Table 25-3.
Table 25-4.
Notes:
11057A–ATARM–17-Feb-12
11057A–ATARM–17-Feb-12
27
27
27
26
26
26
Bk[1:0]
Application Example
1. M0 is the byte address inside a 16-bit half-word.
2. Bk[1] = BA1, Bk[0] = BA0.
25
25
25
Software Interface
Bk[1:0]
Bk[1:0]
16-bit Memory Data Bus Width
24
24
24
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
Bk[1:0]
Bk[1:0]
Bk[1:0]
23
23
23
Bk[1:0]
Bk[1:0]
Bk[1:0]
22
22
22
Bk[1:0]
Bk[1:0]
The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller
allows mapping different memory types according to the values set in the SDRAMC configura-
tion register.
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
user in correlation with the device structure. Various configurations are illustrated.
21
21
21
Bk[1:0]
20
20
20
Table 25-2
19
19
19
Row[12:0]
Row[11:0]
18
18
18
Row[10:0]
Row[12:0]
Row[11:0]
17
17
17
Row[10:0]
Row[12:0]
to
Row[11:0]
16
16
16
Table 25-4
Row[10:0]
Row[12:0]
Row[11:0]
15
15
15
CPU Address Line
CPU Address Line
CPU Address Line
Row[10:0]
14
14
14
illustrate the SDRAM device memory mapping seen by the
13
13
13
12
12
12
11
11
11
10
10
10
9
9
9
8
8
8
7
7
7
Column[10:0]
Column[10:0]
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
6
6
6
Column[8:0]
Column[8:0]
Column[8:0]
Column[7:0]
Column[7:0]
Column[7:0]
5
5
5
4
4
4
SAM3X/A
SAM3X/A
3
3
3
2
2
2
1
1
1
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
M0
405
405
0
0
0
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