ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 90
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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7.9
7.9.1
7.9.2
8331A–AVR–07/11
Register Description - Clock
CTRL – System Clock Control Register
PSCTRL – System Clock Prescaler Register
• Bit 7:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2:0 – SCLKSEL[2:0]: System Clock Selection
These bits are used to select the source for the system clock. See
selections. Changing the system clock source will take two clock cycles on the old clock source
and two more clock cycles on the new clock source. These bits are protected by the configura-
tion change protection mechanism. For details, refer to
page
SCLKSEL cannot be changed if the new clock source is not stable.
Table 7-1.
This register is protected by the configuration change protection mechanism. For details, refer to
”Configuration Change Protection” on page
• Bit 7 – Reserved
This bit is reserved and will always be read as zero. For compatibility with future devices, always
write this bit to zero when this register is written.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
12.
SCLKSEL[2:0]
000
001
010
011
100
101
110
111
R
7
–
0
System clock selection.
R
7
–
0
R/W
6
0
6
–
R
0
R/W
5
0
Group Configuration
R
5
–
0
RC32MHZ
RC32KHZ
RC2MHZ
PSADIV[4:0]
XOSC
PLL
R/W
—
—
—
4
0
R
4
–
0
12.
R/W
Atmel AVR XMEGA AU
3
0
R
3
–
0
”Configuration Change Protection” on
Description
External oscillator or clock
Phase locked loop
Reserved
Reserved
Reserved
2MHz internal oscillator
32MHz internal oscillator
32.768kHz internal oscillator
R/W
R/W
2
0
2
0
SCLKSEL[2:0]
Table 7-1
R/W
R/W
1
0
1
0
PSBCDIV
R/W
for the different
R/W
0
0
0
0
PSCTRL
CTRL
90
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