ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 338
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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27.7.4
27.7.5
27.7.6
27.8
8331A–AVR–07/11
Combined SRAM & SDRAM Configuration
Timing
Initialization
Refresh
The Clock Enable (CKE) signal is required for SDRAM when the EBI is clocked at 2x the CPU
clock speed.
Configuring Chip Select 3 to SDRAM will enable the initialization of the SDRAM. The “Load
Mode Register” command is automatically issued at the end of the initialization. For correct infor-
mation to be loaded to the SDRAM, one must do one of the following:
The SDRAM initialization is non-interruptible by other EBI accesses.
The EBI will automatically handle the SDRAM refresh as long as the refresh period is config-
ured. Refresh will be done as soon as available after the refresh counter reaches the period. The
EBI can collect up to 4 refresh commands in case the interface is busy on another chip select or
in the middle of a read/write at a time a refresh should have been performed.
Combined SRAM and SDRAM configuration enables the EBI to have both SDRAM and SRAM
connected at the same time. This only available when using 4 port EBI interface.
on page 339
– 1.Configure SDRAM control registers before enabling Chip Select 3 to SDRAM.
– 2.Issue a “Load Mode Register” command and perform a dummy-access after
SDRAM is initialized.
shows the configuration with all interface signals.
Atmel AVR XMEGA AU
Figure 27-11
338
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