ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 390

• Manufacturer Part Number: ATxmega128A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega128A3U

• Flash (kbytes): 128 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 8
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

29.10.9
29.10.9.1
29.10.9.2
29.10.10 CH0GAINCAL – Gain Calibration Register
29.10.11 CH0OFFSETCAL – Offset Calibration Register
8331A–AVR–07/11
CH1DATAL – Channel 1 Data Register Low byte
Right-adjusted
Left-adjusted
• Bit 7:0 – CHDATA[7:0]: Conversion Data Register Channel 1, 8 LSB
These bits are the 8LSB of the 12-bit value to convert to channel 1 in right-adjusted mode.
• Bit 7:4 – CHDATA[3:0]: Conversion Data Register Channel 1, 4 LSB
These bits are the 4LSB of the 12-bit value to convert to channel 1 in left-adjusted mode.
• Bit 3:0 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7:0 – CH0GAINCAL[7:0]: Gain Calibration value
These bits are used to compensate the gain error in DAC channel 0. See
384
• Bit 7:0 – CH1OFFSETCAL[7:0]: Offset Calibration value
These bits are used to compensate the offset error in DAC channel 0. See
384
Bit
+0x08 /+0x0A
Read/Write
Initial Value
Bit
+0x09
Read/Write
Initial Value
Right-adjust
Left-adjust
Right-adjust
Left-adjust
Right-adjust
Left-adjust
for details.
for details.
R/W
R/W
7
0
7
0
Bit
+0x1A
Read/Write
Read/Write
Initial Value
Initial Value
R/W
R/W
6
0
6
0
R/W
R/W
R/W
7
0
0
R/W
5
0
5
0
R/W
R/W
CH0OFFSETCAL[7:0]
6
0
0
R/W
CHDATA[3:0]
CH0GAINCAL[7:0]
R/W
4
0
4
0
R/W
R/W
5
0
0
R/W
R/W
3
0
3
0
Atmel AVR XMEGA AU
R/W
R/W
4
0
0
CHDATA[7:0]
R/W
R/W
2
0
2
0
R/W
R
0
0
3
–
R/W
R/W
1
0
1
0
R/W
R
2
–
0
0
”Calibration” on page
”Calibration” on page
R/W
R/W
0
0
0
0
R/W
R
1
–
0
0
CH0OFFSETCAL
CH0GAINCAL
R/W
R
0
–
0
0
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