ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 24
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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4.10.1
4.11
4.12
8331A–AVR–07/11
Memory Timing
Device ID and Revision
Bus Priority
Figure 4-3.
When several masters request access to the same bus, the bus priority is in the following order
(from higher to lower priority):
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes
one cycle, and read from SRAM takes two cycles. For burst read (DMA), new data available
every cycle. EEPROM page load (write) takes one cycle, and three cycles are required for read.
For burst read, new data are available every second cycle. External memory has multi-cycle
read and write. The number of cycles depends on the type of memory and configuration of the
external bus interface. Refer to the instruction summary for more details on instructions and
instruction timing.
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the
device and the device type. A separate register contains the revision number of the device.
1. Bus Master with ongoing access.
2. Bus Master with ongoing burst.
3. Bus Master requesting burst access.
4. Bus Master requesting bus access.
a. Alternating DMA controller read and DMA controller write when they access the
a. CPU has priority.
a. CPU has priority.
Non-Volatile
same data memory section.
EEPROM
Memory
Flash
Bus access.
CH0
CH2
DMA
CH1
CH3
Peripherals and system modules
Controller
Backup
Battery
ADC
DAC
NVM
AC
CRC
AVR core
Management
Event System
Controller
Oscillator
Controller
modules
Interrupt
Control
Crypto
Power
CPU
I/O
Bus matrix
OCD
Real Time
USART
Counter
Counter
Timer /
USB
TWI
SPI
Atmel AVR XMEGA AU
Programming
External
PDI
SRAM
RAM
External
Memory
EBI
24
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