ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 294
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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23.3.3
23.3.4
23.3.5
8331A–AVR–07/11
Double Speed Operation
Synchronous Clock Operation
Master SPI Mode Clock Generation
Double speed operation allows for higher baud rates under asynchronous operation with lower
peripheral clock frequencies. When this is enabled, the baud rate for a given asynchronous baud
rate setting shown in
half the number of samples (reduced from 16 to 8) for data sampling and clock recovery. Due to
the reduced sampling, a more accurate baud rate setting and peripheral clock are required. See
”Asynchronous Data Reception” on page 298
When synchronous mode is used, the XCK pin controls whether the transmission clock is input
(slave mode) or output (master mode). The corresponding port pin must be set to output for
master mode or to input for slave mode. The normal port operation of the XCK pin will be over-
ridden. The dependency between the clock edges and data sampling or data change is the
same. Data input (on RxD) is sampled at the XCK clock edge which is opposite the edge where
data output (TxD) is changed.
Figure 23-3. Synchronous mode XCK timing.
Using the inverted I/O (INVEN) setting for the corresponding XCK port pin, the XCK clock edges
used for data sampling and data change can be selected. If inverted I/O is disabled (INVEN=0),
data will be changed at the rising XCK clock edge and sampled at the falling XCK clock edge. If
inverted I/O is enabled (INVEN=1), data will be changed at the falling XCK clock edge and sam-
pled at the rising XCK clock edge. For more details, see
For master SPI mode operation, only internal clock generation is supported. This is identical to
the USART synchronous master mode, and the baud rate or BSEL setting is calculated using
the same equations (see
There are four combinations of the SPI clock (SCK) phase and polarity with respect to the serial
data, and these are determined by the clock phase (UCPHA) control bit and the inverted I/O pin
(INVEN) settings. The data transfer timing diagrams are shown in
Data bits are shifted out and latched in on opposite edges of the XCK signal, ensuring sufficient
time for data signals to stabilize. The UCPHA and INVEN settings are summarized in
UCPOL = 1
UCPOL = 0
RxD / TxD
RxD / TxD
Table 23-1 on page 293
XCK
XCK
Table 23-1 on page
293).
for more details.
will be doubled. In this mode, the receiver will use
Atmel AVR XMEGA AU
”I/O Ports” on page
Sample
Sample
Figure 23-4 on page
139.
Table 23-2
295.
294
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