ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 417
![no-image](/images/manufacturer_photos/0/0/79/atmel_corporation_sml.jpg)
ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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32.4.5
32.4.6
8331A–AVR–07/11
Serial transmission and reception
Serial Transmission
Figure 32-11. Special data characters.
The JTAG interface supports full-duplex communication. At the same time as input data is
shifted in on the TDI pin, output data is shifted out on the TDO pin. However, PDI communica-
tion relies on half-duplex data transfer. Due to this, the JTAG physical layer operates only in
either transmit (TX) or receive (RX) mode. The available JTAG bit channel is used for control
and status signalling.
The programmer and the JTAG interface operate synchronously on the TCK clock provided by
the programmer. The dependency between the clock edges and data sampling or data change
is fixed. As illustrated in
the falling edge of TCK, while data always should be sampled on the rising edge of TCK.
Figure 32-12. Changing and sampling data.
When data transmission is initiated, a data byte is loaded into the shift register and then out on
TDO. The parity bit is generated and appended to the data byte during transmission. The trans-
mission speed is given by the TCK signal.
If the PDI is in TX mode (as a response to an LD instruction), and a transmission request from
the PDI controller is pending when the TAP controller enters the capture DR state, valid data will
be parallel-loaded into the shift register, and a correct parity bit will be generated and transmitted
along with the data byte in the shift DR state.
If the PDI is in RX mode when the TAP controller enters the capture DR state, an EMPTY byte
will be loaded into the shift register, and the parity bit will be set (forcing a parity error) when data
is shifted out in the shift DR state. This situation occurs during normal PDI command and oper-
and reception.
TD I/TDO
TC K
Figure 32-12 on page
1
1
1
1
1
1
1 EMPTY CHARACTER (EB+P1)
1 BREAK CHARACTER (BB+P1)
1 DELAY CHARACTER (DB+P1)
0
0
0
S am ple
1
1
1
1
1
0
417, TDI and TDO is always set up (change) on
Atmel AVR XMEGA AU
1
0
1
S am ple
0
1
1
1
1
1
P1
P1
P1
S am ple
417
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