ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 117
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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9.5
9.5.1
9.5.2
8331A–AVR–07/11
Register Description
STATUS – Reset Status Register
CTRL – Reset Control Register
• Bit 7:6 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 5 – SRF: Software Reset Flag
This flag is set if a software reset occurs. The flag will be cleared by a power-on reset or by writ-
ing a one to the bit location.
• Bit 4 – PDIRF: Program and Debug Interface Reset Flag
This flag is set if a programming interface reset occurs. The flag will be cleared by a power-on
reset or by writing a one to the bit location.
• Bit 3 – WDRF: Watchdog Reset Flag
This flag is set if a watchdog reset occurs. The flag will be cleared by a power-on reset or by writ-
ing a one to the bit location.
• Bit 2 – BORF: Brownout Reset Flag
This flag is set if a brownout reset occurs. The flag will be cleared by a power-on reset or by writ-
ing a one to the bit location.
• Bit 1 – EXTRF: External Reset Flag
This flag is set if an external reset occurs. The flag will be cleared by a power-on reset or by writ-
ing a one to the bit location.
• Bit 0 – PORF: Power On Reset Flag
This flag is set if a power-on reset occurs. Writing a one to the flag will clear the bit location.
• Bit 7:1 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0 – SWRST: Software Reset
When this bit is set, a software reset will occur. The bit is cleared when a reset is issued. This bit
is protected by the configuration change protection mechanism. For details, refer to
tion Change Protection” on page
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
R
7
–
0
R
7
–
-
R
6
–
0
6
–
R
-
SRF
R/W
R
5
–
0
12.
5
-
PDIRF
R/W
R
4
–
0
4
-
WDRF
Atmel AVR XMEGA AU
R/W
R
3
–
0
3
-
BORF
R/W
R
2
–
0
2
-
EXTRF
R/W
1
–
R
0
1
-
SWRST
PORF
R/W
R/W
0
0
0
-
”Configura-
STATUS
CTRL
117
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