ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 414
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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32.3.6
32.3.7
Figure 32-7. PDI direction change by inserting IDLE bits.
32.3.8
8331A–AVR–07/11
t S
Serial Reception
Direction Change
Drive Contention and Collision Detection
PDI DATA Receive (RX)
When a start bit is detected, the receiver starts to collect the eight data bits. If the parity bit does
not correspond to the parity of the data bits, a parity error has occurred. If one or both of the stop
bits are low, a frame error has occurred. If the parity bit is correct, and no frame error is detected,
the received data bits are available for the PDI controller.
When the PDI is in TX mode, a BREAK character signaled by the programmer will not be inter-
preted as a BREAK, but will instead cause a generic data collision. When the PDI is in RX mode,
a BREAK character will be recognized as a BREAK. By transmitting two successive BREAK
characters (which must be separated by one or more high bits), the last BREAK character will
always be recognized as a BREAK, regardless of whether the PDI was in TX or RX mode ini-
tially. This is because in TX mode the first BREAK is seen as a collision. The PDI then shifts to
RX mode and sees the second BREAK as break.
In order to ensure correct timing for half-duplex operation, a guard time mechanism is used.
When the PDI changes from RX mode to TX mode, a configurable number of IDLE bits are
inserted before the start bit is transmitted. The minimum transition time between RX and TX
mode is two IDLE cycles, and these are always inserted. The default guard time value is 128
bits.
1 DATA character
The external programmer will loose control of the PDI_DATA line at the point where the PDI
changes from RX to TX mode. The guard time relaxes this critical phase of the communication.
When the programmer changes from RX mode to TX mode, a single IDLE bit, at minimum,
should be inserted before the start bit is transmitted.
In order to reduce the effect of drive contention (the PDI and the programmer driving the
PDI_DATA line at the same time), a mechanism for collision detection is used. The mechanism
is based on the way the PDI drives data out on the PDI_DATA line. As shown in
page
Hence, if two or more successive bit values are the same, the value is actively driven only on the
first clock cycle. After this point, the PDI output driver is automatically tri-stated, and the
PDI_DATA pin has a bus keeper responsible for keeping the pin value unchanged until the out-
put driver is reenabled due to a change in the bit value.
Programmer to
PDI interface
Data from
415, the PDI output driver is active only when the output value changes (from 0-1 or 1-0).
P
Sp1
Sp2
Dir. change
IDLE bits
Guard time
# IDLE bits
inserted
t S
Atmel AVR XMEGA AU
PDI DATA Transmit (TX)
1 DATA character
to Programmer
PDI interface
Data from
P
Figure 32-8 on
Sp1 Sp2
414
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