ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 59
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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5.13.5
5.14
5.14.1
8331A–AVR–07/11
Register Description – DMA Channel
TEMPH – DMA Temporary Register High
CTRLA – DMA Channel Control Register A
• Bit 7:0 – TEMP[15:8]: DMA Temporary Register
This register is used when reading and writing 24-bit registers in the DMA controller. Byte 2 of
the 24-bit register is stored when it is written by the CPU. Byte 2 of the 24-bit register is stored
here when byte 1 is read by the CPU. This register can also be read and written from the user
software.
Reading and writing 24-bit registers requires special attention. For details, refer to
16-bit Registers” on page
• Bit 7 – CHEN: DMA Channel Enable
Setting this bit enables the DMA channel. This bit is automatically cleared when the transaction
is completed. If the DMA channel is enabled and this bit is written to zero, the CHEN bit is not
cleared until the internal transfer buffer is empty and the DMA transfer is aborted.
• Bit 6 – CHRST: DMA Channel Software Reset
Setting this bit will reset the DMA channel. It can only be set when the DMA channel is disabled
(CHEN = 0). Writing a one to this bit will be gnored as long as the channel is enabled (CHEN=1).
This bit is automatically cleared when reset is completed.
• Bit 5 – REPEAT: DMA Channel Repeat Mode
Setting this bit enables the repeat mode. In repeat mode, this bit is cleared by hardware at the
beginning of the last block transfer. The REPCNT register should be configured before setting
the REPEAT bit.
• Bit 4 – TRFREQ: DMA Channel Transfer Request
Setting this bit requests a data transfer on the DMA channel. This bit is automatically cleared at
the beginning of the data transfer. Writing this bit does not have any effect unless the channel is
enabled.
• Bit 3 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x07
Read/Write
Initial Value
CHEN
R/W
R/W
7
0
7
0
CHRST
R/W
R/W
6
0
6
0
12.
REPEAT
R/W
R/W
5
0
5
0
TRFREQ
R/W
R/W
4
0
4
0
TEMP[15:8]
Atmel AVR XMEGA AU
R/W
3
0
R
3
–
0
SINGLE
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
BURSTLEN[1:0]
0
R/W
R/W
0
0
0
0
”Accessing
TEMPH
CTRLA
59
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