ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 198
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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15.10.8
15.10.9
8331A–AVR–07/11
INTFLAGS — Interrupt Flag Register
CNTL – Count Register Low
• Bit 1:0 – CMDEN[1:0]: Command Enable
These bits are used to indicate for which Timer/Counter the command (CMD) is valid.
Table 15-5.
• Bit 7:4 – CMPLxIF: Compare or Capture channel x Interrupt Flag
The Compare Interrupt Flag (CMPLxIF) is set on a compare match on the corresponding CMP
channel.
For all modes of operation the CMPLxIF will be set when a compare match occurs between the
count register (CNTL) and the corresponding compare register (CMPLx). The CMPLxIF is auto-
matically cleared when the corresponding interrupt vector is executed. The flag can also be
cleared by writing a one to its bit location.
• Bit 3:2 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 1 – UNFHIF: High Byte Timer Underflow Interrupt Flag
The UNFHIF is set either on a BOTTOM (underflow) condition. The UNFHIF is automatically
cleared when the corresponding interrupt vector is executed. The flag can also be cleared by
writing a one to its bit location.
• Bit 0 – UNFLIF: Low Byte Timer Underflow Interrupt Flag
The UNFLIF is set either on a BOTTOM (underflow) condition. The UNFLIF is automatically
cleared when the corresponding interrupt vector is executed. The flag can also be cleared by
writing a one to its bit location.
• Bit 7:0 – CNTL[7:0]
CNTL contains the 8-bit counter value for the Low Byte Timer/Counter. The CPU and DMA write
access has priority over count, clear, or reload of the counter.
Bit
+0x0C
Read/Write
Initial Value
Bit
+0x20
Read/Write
Initial Value
CMD
00
01
10
11
CMPLDIF
R/W
R/W
Command selections
7
0
7
0
—
LOW
HIGH
BOTH
Group Configuration
CMPLCIF
R/W
R/W
6
0
6
0
CMPLBIF
R/W
R/W
5
0
5
0
CMPLAIF
Description
Reserved
Command valid for Low Byte T/C
Command valid for High Byte T/C
Command valid for both Low Byte and High Byte T/C
R/W
R/W
4
0
4
0
CNTL[7:0]
Atmel AVR XMEGA AU
R/W
R
3
–
0
3
0
R/W
R
2
–
0
2
0
UNFHIF
R/W
R/W
1
0
1
0
UNFLIF
R/W
R/W
0
0
0
0
INTFLAGS
CNTL
198
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