ATxmega128A3U Atmel Corporation, ATxmega128A3U Datasheet - Page 369
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ATxmega128A3U
Manufacturer Part Number
ATxmega128A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega128A3U
Flash (kbytes)
128 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega128A3U-AU
Manufacturer:
ATMEL
Quantity:
39
Company:
Part Number:
ATxmega128A3U-MH
Manufacturer:
ATMEL
Quantity:
1
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8331A–AVR–07/11
Table 28-6.
• Bit 5:3 – EVSEL[2:0]: event channel input select
These bits select which event channel will trigger which ADC channel. Each setting defines a
group of event channels, where the event channels with the lowest number will trigger ADC
channel 0 and the next event channel will trigger ADC channel 1 and so on. See
page
Table 28-7.
• Bit 2:0 – EVACT[2:0]: ADC Event Mode
These bits select and limit how many of the selected event input channel that are used and also
limits the ADC Channels triggers further. It also defines more specialised event triggers as
defined in
Table 28-8.
EVACT[2:0]
000
001
010
011
100
SWEEP[1:0]
369.
EVSEL[2:0]
000
001
010
011
100
101
110
111
00
01
10
11
Table 28-7 on page
ADC Channel Select
ADC Event Channel Select
ADC Event Mode Select
Group Configuration
CH0123
CH012
NONE
CH01
CH0
Group Configuration
Group Configuration
369.
0123
0123
1234
2345
3456
4567
012
567
01
67
0
7
Event input operation mode
No event inputs
Event channel with the lowest number, defined by EVSEL
triggers conversion on ADC channel 0
Event channel with the two lowest numbers, defined by EVSEL
trigger conversion on ADC channel 0 and 1 respectively
Event channel with the three lowest numbers, defined by
EVSEL trigger conversion on ADC channel 0, 1 and 2
respectively
Event channel defined by EVSEL trigger conversion on ADC
channel 0, 1, 2 and 3 respectively
Active ADC channels for channel sweep
Only ADC channel 0
ADC channels 0 and 1
ADC channels 0, 1, and 2
ADC channels 0, 1, 2, and 3
Selected event lines
Event channel 0, 1, 2, 3 as selected inputs
Event channel 1, 2, 3, 4 as selected inputs
Event channel 2, 3, 4, 5 as selected inputs
Event channel 3, 4, 5, 6 as selected inputs
Event channel 4, 5, 6, 7 as selected inputs
Event channel 5, 6, 7 as selected inputs
Event channel 6, 7 as selected inputs
Event channel 7 as selected input
Atmel AVR XMEGA AU
Table 28-7 on
369
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