AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 899
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
32117C–AVR-08/11
TXOUTI
FIFOCON
TXOUTI
FIFOCON
TXOUTI shall be cleared by software to acknowledge the interrupt. This is done by writing a one
to the Transmitted OUT Data Interrupt Clear bit (UPCONnCLR.TXOUTIC), which does not affect
the pipe FIFO.
The user writes the OUT data to the bank referenced to by the PEPn descriptor and allows the
USBC to send the data by writing a one to the FIFO Control Clear (UPCONnCLR.FIFOCONC)
bit. This will also cause a switch to the next bank if the OUT pipe is composed of multiple banks.
The TXOUTI and FIFOCON bits will be updated accordingly
TXOUTI shall always be cleared before clearing FIFOCON to avoid missing an TXOUTI event.
Note that if the user decides to switch to the Suspend state (by writing a zero to UHCON.SOFE)
while a bank is ready to be sent, the USBC automatically exits this state and sends the data.
Figure 32-21. Example of an OUT pipe with one data bank
Figure 32-22. Example of an OUT pipe with two data banks and no bank switching delay
SW
SW
write data to CPU
write data to CPU
BANK 0
BANK 0
SW
OUT
SW
OUT
SW
(bank 0)
DATA
write data to CPU
BANK 1
(bank 0)
DATA
ACK
HW
HW
ACK
SW
OUT
SW
SW
write data to CPU
(bank 1)
DATA
write data to CPU
BANK 0
BANK0
AT32UC3C
ACK
SW
OUT
899
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