AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 897

• Manufacturer Part Number: AT32UC3C164C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C164C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.6.3.9
32.6.3.10
32.6.3.11
32117C–AVR-08/11
Multi packet mode and single packet mode.
Management of control pipes
Management of IN pipes
• Overview
• Detailed description
See
pipe corresponds to an IN endpoint, and an IN pipe corresponds to an OUT endpoint.
A control transaction is composed of three stages:
The user has to change the pipe token according to each stage.
For control pipes only, the token is assigned a specific initial data toggle sequence:
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be read, acknowledging whether or not the bank is empty.
The pipe and its descriptor in RAM must be pre configured.
The host can request data from the device in two modes, selected by writing to the IN Request
Mode bit in the Pipe n IN Request register (UPINRQn.INMODE):
The generation of IN requests starts when the pipe is unfrozen (UPCONn.PFREEZE is zero).
When the current bank is full, the RXINI and FIFO Control (UPSTAn.FIFOCON) bits will be set
simultaneously. This triggers a PnINT interrupt if the Received IN Data Interrupt Enable bit
(UPCONn.RXINE) is one.
RXINI shall be cleared by software to acknowledge the interrupt. This is done by writing a one to
t h e R e c e i v e d I N D a t a I n t e r r u p t C l e a r b i t i n t h e P i p e n C o n t r o l C l e a r r e g i s t e r
(UPCONnCLR.RXINIC), which does not affect the pipe FIFO.
T h e u s e r r e a d s t h e b y t e c o u n t o f t h e c u r r e n t b a n k f r o m t h e d e s c r i p t o r i n R A M
(Pn_PCKSIZE_BK0/1.BYTE_COUNT) to know how many bytes should be read.
The user reads the IN data from the RAM and clears the FIFOCON bit to free the bank. This will
also cause a switch to the next bank if the IN endpoint is composed of multiple banks. The RXINI
and FIFOCON bits will be updated accordingly.
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
• SETUP: Data0
• IN: Data1
• OUT: Data1
• When INMODE is written to zero, the USBC will perform INRQ IN requests before freezing
• When INMODE is written to one, the USBC will perform IN requests as long as the pipe is not
the pipe.
frozen by the user.
”Multi packet mode and single packet mode.” on page 884
– DTGLER: Is set if a Data toggle error occurs during a USB transaction.
and just consider that an OUT
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