AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 412

• Manufacturer Part Number: AT32UC3C164C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C164C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

21.4.4
21.4.5
21.4.6
21.5
32117C–AVR-08/11
Single Transfer Mode
Aborting Transfers
Interrupts
Bus Errors
In Round-Robin Mode, other channels with transfers pending will preempt the current channel in
a round-robin fashion. This eliminates the possibility of starvation.
Transfers on any channel can be gracefully aborted by writing a one to the corresponding Chan-
nel Disable bit in the Control Register (CR.CHxDIS). Note that in order to successfully write to
CHxDIS, the same write operation must also write a one to the corresponding Channel Enable
bit (CR.CHxEN). Successfully writing to CHxDIS will result in both CHxEN and CHxDIS being
cleared. CHxEN can not be cleared by simply writing a zero to it.
The hardware will disable the transfer as soon as possible. Since the transfer must terminate
gracefully, the CHxEN bits may not be cleared immediately after writing CHxDIS. The user could
poll CHxDIS to check when the channel has been disabled.
The MDMA can generate an interrupts when a channel has completed a transfer or when a DMA
transfer causes a bus error. Interrupts are only generated if enabled in the Interrupt Mask Regis-
ter (IMR). IMR is read-only, but can be modified through the write-only Interrupt Enable Register
(IER) and Interrupt Disable Register (IDR). An interrupt is enabled by writing a one to the corre-
sponding bit in the IER. An interrupt is disabled by writing a one to the corresponding bit in the
IDR. If an interrupt occurs, the corresponding bit in the Interrupt Status Register (ISR) is set and
an interrupt request is generated. Bits in ISR and their corresponding interrupt request can be
cleared by writing to the appropriate bits in the Interrupt Clear Register (ICR).
Any bus errors from transfers on a channel will automatically disable the channel. Other chan-
nels will not be affected by this. An interrupt is generated if not masked by the Interrupt Mask
Register (IMR).
The Single Transfer Mode (STM) is the simplest transfer mode. The software programs the reg-
isters controlling the channel, writes the correct enable bit (CR.CHxEN), and the transfer starts.
The transfer can be preempted if a channel with higher priority is enabled before the transfer
completes, or if we use Round-Robin Mode.
When the transfer completes, the CR.CHxEN bit is automatically cleared. If the Channel Com-
plete interrupt is enabled in IMR (IMR.CHxC is one), an interrupt request is generated.
In order to perform a transfer in STM, the following steps must be performed:
1. Make sure that the channel is free by checking the CR.CHxEN bit, or by waiting for a
2. Set up the Read Address Register (RARx), Write Address Register (WARx) and Chan-
3. Enable the desired interrupts by writing a one to the corresponding bits in the Interrupt
4. Write a one to CR.CHxEN to start the transfer. Make sure the Channel Mode bit
5. When the transfer completes, the CHxEN bit is automatically cleared. If the Channel
Transfer Complete interrupt from the channel.
nel Control Register (CCRx) associated with the channel.
Enable Register (IER).
(CR.CHxM) for the channel is zero (channel is in Single Transfer Mode)
Complete interrupt for the channel is enabled, the corresponding bit in the Interrupt Sta-
tus Register (ISR.CHxC) is set.
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