AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 858

• Manufacturer Part Number: AT32UC3C164C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C164C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

31.7.8
Name:
Access Type:
Offset:
Reset Value:
Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
• MTIOB: TIOB Mirror
• MTIOA: TIOA Mirror
• CLKSTA: Clock Enabling Status
• ETRGS: External Trigger Status
• LDRBS: RB Loading Status
• LDRAS: RA Loading Status
• CPCS: RC Compare Status
32117C–AVR-08/11
ETRGS
31
23
15
7
-
-
-
1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven
high.
0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven
low.
1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven
high.
0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven
low.
1: This bit is set when the clock is enabled.
0: This bit is cleared when the clock is disabled.
1: This bit is set when an external trigger has occurred.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
1: This bit is set when an RC Compare has occurred.
0: This bit is cleared when the SR register is read.
Channel Status Register
LDRBS
30
22
14
6
-
-
-
SR
Read-only
0x20 + n * 0x40
0x00000000
LDRAS
29
21
13
5
-
-
-
CPCS
28
20
12
4
-
-
-
CPBS
27
19
11
3
-
-
-
MTIOB
CPAS
26
18
10
2
-
-
LOVRS
MTIOA
25
17
9
1
-
-
AT32UC3C
CLKSTA
COVFS
24
16
8
0
-
-
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