AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 53

• Manufacturer Part Number: AT32UC3C164C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C164C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.6.1.3
7.6.2
7.6.2.1
7.6.3
7.6.3.1
32117C–AVR-08/11
Peripheral Clock Masking
Sleep Modes
Clock Ready flag
Cautionary note
Entering and exiting sleep modes
Similarly, the clock for the PBx can be divided by writing their respective registers. To ensure
correct operation, frequencies must be selected so that f
exceed the specified maximum frequency for each clock domain.
CPUSEL and PBxSEL can be written without halting or disabling peripheral modules. Writing
CPUSEL and PBxSEL allows a new clock setting to be written to all synchronous clocks at the
same time. It is possible to keep one or more clocks unchanged by writing a one to the registers.
This way, it is possible to, e.g., scale CPU and HSB speed according to the required perfor-
mance, while keeping the PBx frequency constant.
For modules connected to the HSB bus, the PB clock frequency must be set to the same fre-
quency as the CPU clock.
There is a slight delay from CPUSEL and PBxSEL is written and the new clock setting becomes
effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as zero. If CKRDY
in the IER register is written to one, the Power Manager interrupt can be triggered when the new
clock setting is effective. CKSEL must not be re-written while CKRDY is zero, or the system may
become unstable or hang.
By default, the clock for all modules are enabled, regardless of which modules are actually being
used. It is possible to disable the clock for a module in the CPU, HSB or PBx clock domain by
writing the corresponding bit in the Clock Mask register (CPU/HSB/PBx) to zero. When a module
is not clocked, it will cease operation, and its registers cannot be read or written. The module
can be re-enabled later by writing the corresponding mask bit to one.
A module may be connected to several clock domains, in which case it will have several mask
bits.
The Maskable Module Clocks table contains a list of implemented maskable clocks.
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the flash controller will cause a problem if the CPU needs to read from
the flash. Switching off the clock to the Power Manager (PM), which contains the mask registers,
or the corresponding PBx bridge, will make it impossible to write the mask registers again. In this
case, they can only be re-enabled by a system reset.
In normal operation, all clock domains are active, allowing software execution and peripheral
operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other
clock domains to save power. This is activated by the sleep instruction, which takes the sleep
mode index number from
The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.
The modules will be halted regardless of the bit settings of the mask registers.
Clock sources can also be switched off to save power. Some of these have a relatively long
start-up time, and are only switched off when very low power consumption is required.
Table 7-2 on page 54
as argument.
CPU
≥ f
PBx
. Also, frequencies must never
AT32UC3C
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