AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 1105
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
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36.5.6
36.6
36.6.1
36.6.2
36.6.2.1
36.6.2.2
32117C–AVR-08/11
Functional Description
Debug Operation
ADC Resolution
ADC Conversion Modes
S/H versus DIRECT conversions
Differential / single ended
When an external debugger forces the CPU into debug mode:
The ADC supports 8-bit, 10-bit or 12 bits resolutions. Precision can be set differently for each
sequencer by setting the SRES bits in the SEQCFGx register. By default, after a reset, the reso-
lution is set to 12 bits. To get full resolution, the user should first calibrate the ADC as detailed in
Section
The ADC is fully differential. To perform single ended measures, the user can perform pseudo
unipolar conversions by connecting ground onto the negative input. User can connect it to an
external ground through pads or internal ground depending on if there's one connected onto the
negative input multiplexer. Since conversion results are always 12 bits in 2's complement repre-
sentation, the sign bit will not change, and then the resulting resolution is 11 bits max.
By default S/H are enabled, to change that setting, set the Sample and Hold disable bit (SHD)
located in the CFG register. Maximum accuracy is achieved when disabling S/H but setting this
bit forbids dual sequencer mode, Sequencer 1 is then switched off. Furthermore, in this mode
S/H are switched off to lower power consumption.
Table 36-2.
S/H
DIRECT
• the ADCIFA continues normal operation if the bit related to ADCIFA in PDBG register is ‘0’.
• the ADCIFA is frozen if the bit related to ADCIFA in PDBG register is ‘1’. When the ADCIFA is
PDCA access continues normal operation and may interfere with debug operation.
frozen, ADCIFA PB registers can still be accessed. Then, reading registers may modify
status bits (OVRx, LOVRx) like in normal operation. PDCA access are pending.
Mode
36.6.16.
Characteristics
Pros
Cons
Pros
Cons
S/H versus DIRECT Conversions
Gain setting (1, 2, 4, 8, 16, 32, 64)
Dual sequencer mode
Reduced accuracy
Dynamic limitation (fixed with over-sampling)
1 ADC clock period spent to propagate into S/H
No dynamic limitation due to S/H
Full accuracy
Saves 1 ADC clock period compared to the features list timings
No gain
Single sequencer mode only
AT32UC3C
1105
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