AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 58

• Manufacturer Part Number: AT32UC3C164C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C164C

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 20
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7.7
Table 7-5.
32117C–AVR-08/11
0x00010
0x00CC
0x000C
0x002C
0x00C0
0x00C4
0x00C8
0x00D0
0x00D4
0x03FC
0x0000
0x0004
0x0008
0x0014
0x0020
0x0024
0x0028
0x0030
0x0040
0x0044
0x0048
0x0054
0x0058
0x0180
0x0184
0x0188
0x03F8
Offset
User Interface
PM Register Memory Map
Note:
Clock Failure Detector Control
PM Interrupt Disable Register
PM Interrupt Enable Register
PM Interrupt Status Register
Asynchronous Wake Enable
PM Interrupt Mask Register
PM Interrupt Clear Register
Configuration Register
Reset Cause Register
Wake Cause Register
Main Clock Control
PBA Divided Mask
PBB Divided Mask
PBC Divided Mask
CPU Clock Select
HSB Clock Select
PBA Clock Select
PBB Clock Select
PBC Clock Select
Version Register
1. The reset value is device specific. Please refer to the Module Configuration section at the end
Unlock Register
Status Register
CPU Mask
HSB Mask
PBA Mask
PBB Mask
PBC Mask
Register
of this chapter.
PBADIVMASK
PBBDIVMASK
PBCDIVMASK
CPUMASK
HSBMASK
PBAMASK
PBBMASK
PBCMASK
CFDCTRL
VERSION
WCAUSE
MCCTRL
UNLOCK
CPUSEL
RCAUSE
HSBSEL
PBASEL
PBBSEL
PBCSEL
CONFIG
AWEN
Name
IMR
IER
IDR
ISR
ICR
SR
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
Read Only
Read Only
Write Only
Write Only
Write Only
Read Only
Write Only
Read Only
Read Only
Read Only
Read Only
Access
Latest Reset Source
Latest Wake Source
AT32UC3C
0x07FFFFFF
0x00003FFF
0x0000007F
0x000003FF
0x0000007F
0x0000007F
0x0000007F
Reset State
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000003
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
-
-
(1)
(1)
-
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