AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 230

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AT32UC3C164C

Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of AT32UC3C164C

Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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14.7
PEVC Register Memory Map
Notes:
32117C–AVR-08/11
0x200 + m*0x004
0x100 + n*0x004
0x0C0 - 0x0C4
0x0D0 - 0x0D4
0x0A0 - 0x0A4
0x0B0 - 0x0B4
0x0E0 - 0x0E4
0x0F0 - 0x0F4
0x010 - 0x014
0x020 - 0x024
0x030 - 0x034
0x040 - 0x044
0x050 - 0x054
0x060 - 0x064
0x070 - 0x074
0x080 - 0x084
0x090 - 0x094
User Interface
0x1FC
0x2FC
1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this
2. i={0,1}, where i=0 contains the lowest 32 channels, and i=1 contains the highest 32 channels. The lowest address contains
Offset
0x000
0x004
0x008
0x100
0x200
chapter.
register 0, the highest address contains register 1. Register 1 is only implemented if the device has more than 32 channels
implemented. Please refer to the Module Configuration section at the end of this chapter for details.
Overrun Interrupt Mask Disable Register
Overrun Interrupt Mask Enable Register
Trigger Interrupt Mask Disable Register
Trigger Interrupt Mask Enable Register
Input Glitch Filter Divider Register
Overrun Interrupt Mask Register
Trigger Interrupt Mask Register
Overrun Status Clear Register
Trigger Status Clear Register
Channel Disable Register
Channel Enable Register
Channel Status Register
Overrun Status Register
Trigger Status Register
Channel Multiplexer 63
Channel Multiplexer 0
Channel Multiplexer n
Channel / User Busy
Event Shaper 63
Event Shaper m
Event Shaper 0
Software Event
Parameter
Register
Version
Register Name
PARAMETER
OVSCRi
VERSION
TRSCRi
OVIMRi
TRIMRi
TRIDRi
OVIERi
OVIDRi
TRIERi
CHMX63
CHSRi
CHERi
CHDRi
OVSRi
BUSYi
TRSRi
CHMX0
CHMXn
IGFDR
SEVi
EVS63
EVSm
EVS0
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Write-only
Access
AT32UC3C
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Reset
-
-
-
(1)
(1)
(1)
-
-
-
-
-
-
-
-
-
230

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