AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 952

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.7.3.11
Register Name:
Access Type:
Offset:
Reset Value:
• CURRBK: Current Bank
• NBUSYBK: Number of Busy Banks
• RAMACERI: Ram Access Error Interrupt
32117C–AVR-08/11
31
23
15
7
-
-
-
-
For non-control pipe, this field indicates the number of the current bank.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field for an interrupt.
This field indicates the number of busy bank.
For OUT pipe, this field indicates the number of busy bank(s), filled by the user, ready for OUT transfer. When all banks are
busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
For IN pipe, this field indicates the number of busy bank(s) filled by IN transaction from the Device. When all banks are free, this
triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
This bit is cleared when the RAMACERIC bit is written to one.
This bit is set when a RAM access underflow error occurs during IN data stage.
0
0
0
0
1
1
Pipe n Status Register
NBUSYBK
CURRBK
RXSTALLDI/
CRCERRI
CURRBK
30
22
14
6
-
-
UPSTAn, n in [0..6]
Read-Only
0x0530 + (n * 0x04)
0x00000000
0
1
0
1
0
1
ERRORFI
29
21
13
5
-
-
Current Bank
Bank0
Bank1
Number of busy bank
All banks are free.
1 busy bank
2 busy banks
reserved
NBUSYBK
NAKEDI
28
20
12
4
-
-
PERRI
27
19
11
3
-
-
-
RAMACERI
TXSTPI
26
18
10
2
-
-
TXOUTI
25
17
9
1
-
-
DTSEQ
AT32UC3C
RXINI
24
16
8
0
-
-
952