AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 945

• Manufacturer Part Number: AT32UC3C1512C
• Manufacturer: Atmel Corporation

Specifications of AT32UC3C1512C

• Flash (kbytes): 512 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 81
• Ext Interrupts: 100
• Usb Transceiver: 1
• Quadrature Decoder Channels: 2
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 7
• Twi (i2c): 3
• Uart: 5
• Can: 2
• Lin: 5
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 4
• Dac Resolution (bits): 12
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 68
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6 or 4.5 to 5.5
• Operating Voltage (vcc): 3.0 to 3.6 or 4.5 to 5.5
• Fpu: Yes
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 22
• Input Capture Channels: 12
• Pwm Channels: 19
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32.7.3.5
Register Name:
Access Type:
Offset:
Reset Value:
Note:
• PnINTE: Pipe n Interrupt Enable
• HWUPIE: Host Wakeup Interrupt Enable
• HSOFIE: Host Start of Frame Interrupt Enable
• RXRSMIE: Upstream Resume Received Interrupt Enable
• RSMEDIE: Downstream Resume Sent Interrupt Enable
• RSTIE: USB Reset Sent Interrupt Enable
• DDISCIE: Device Disconnection Interrupt Enable
• DCONNIE: Device Connection Interrupt Enable
32117C–AVR-08/11
P7INTE
31
23
15
7
-
-
-
1. PnINTE bits are within the range from P0INTE to P6INTE.
This bit is cleared when the PnINTEC bit is written to one. This will disable the Pipe n Interrupt (PnINT).
This bit is set when the PnINTES bit is written to one. This will enable the Pipe n Interrupt (PnINT).
This bit is cleared when the HWUPIEC bit is written to one. This will disable the Host Wakeup Interrupt (HWUPI).
This bit is set when the HWUPIES bit is written to one. This will enable the Host Wakeup Interrupt (HWUPI).
This bit is cleared when the HSOFIEC bit is written to one. This will disable the Host Start of Frame interrupt (HSOFI).
This bit is set when the HSOFIES bit is written to one. This will enable the Host Start of Frame interrupt (HSOFI).
This bit is cleared when the RXRSMIEC bit is written to one. This will disable the Downstream Resume interrupt (RXRSMI).
This bit is set when the RXRSMIES bit is written to one. This will enable the Upstream Resume Received interrupt (RXRSMI).
This bit is cleared when the RSMEDIEC bit is written to one. This will disable the Downstream Resume interrupt (RSMEDI).
This bit is set when the RSMEDIES bit is written to one. This will enable the Downstream Resume interrupt (RSMEDI).
This bit is cleared when the RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (RSTI).
This bit is set when the RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (RSTI).
This bit is cleared when the DDISCIEC bit is written to one. This will disable the Device Disconnection interrupt (DDISCI).
This bit is set when the DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (DDISCI).
This bit is cleared when the DCONNIEC bit is written to one. This will disable the Device Connection interrupt (DCONNI).
This bit is set when the DCONNIES bit is written to one. This will enable the Device Connection interrupt (DCONNI).
(1)
Host Global Interrupt Enable Register
P6INTE
HWUPIE
30
22
14
6
-
-
UHINTE
Read-Only
0x0410
0x00000000
(1)
P5INTE
HSOFIE
29
21
13
5
-
-
(1)
RXRSMIE
P4INTE
28
20
12
4
-
-
(1)
RSMEDIE
P3INTE
27
19
11
3
-
-
(1)
P2INTE
RSTIE
26
18
10
2
-
-
(1)
P1INTE
DDISCIE
25
17
9
1
-
-
(1)
AT32UC3C
DCONNIE
P8INTE
P0INTE
24
16
8
0
-
(1)
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