AT32UC3C1512C Atmel Corporation, AT32UC3C1512C Datasheet - Page 647
AT32UC3C1512C
Manufacturer Part Number
AT32UC3C1512C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C1512C
Flash (kbytes)
512 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
68
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
25.7.16
Name:
Access Type:
Offset:
Reset Value:
•
•
•
•
•
•
•
•
•
32117C–AVR-08/11
SYNCDIS: Synchronization Disable
PDCM: Peripheral DMA Controller Mode
DLC: Data Length Control
WKUPTYP: Wakeup Signal Type
FSDIS: Frame Slot Mode Disable
DLM: Data Length Mode
CHKTYP: Checksum Type
CHKDIS: Checksum Disable
PARDIS: Parity Disable
WKUPTYP
31
23
15
–
–
7
0: The Synchronization procedure is performed in LIN Slave node configuration.
1: The Synchronization procedure is not performed.
0: The LIN mode register LINMR is not written by the Peripheral DMA Controller.
1: The LIN mode register LINMR (excepting that bit) is written by the Peripheral DMA Controller.
0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes.
0: setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal.
1: setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal.
0: The Frame Slot Mode is enabled.
1: The Frame Slot Mode is disabled.
0: The response data length is defined by the field DLC of this register.
1: The response data length is defined by the bits 4 and 5 of the Identifier (IDCHR in LINIR).
0: LIN 2.0 “Enhanced” Checksum
1: LIN 1.3 “Classic” Checksum
0: In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the checksum
1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked.
0: In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node
1:Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked.
is checked automatically.
configuration, the parity is checked automatically.
LIN Mode Register
FSDIS
30
22
14
LINMR
Read-write
0x54
0x00000000
–
–
6
DLM
29
21
13
–
–
5
CHKTYP
28
20
12
–
–
4
DLC
CHKDIS
27
19
11
–
–
3
PARDIS
26
18
10
–
–
2
SYNCDIS
25
17
–
9
1
AT32UC3C
NACT
PDCM
24
16
–
8
0
647
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