AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 540

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

24.9.13
Name:
Access Type:
Offset:
Reset value:
• RXEN: Receive Enable
• TXEN: Transmit Enable
• RXSYN: Receive Sync
• TXSYN: Transmit Sync
• CP1: Compare 1
• CP0: Compare 0
• OVRUN: Receive Overrun
• RXRDY: Receive Ready
• TXEMPTY: Transmit Empty
32072G–11/2011
31
23
15
7
-
-
-
-
This bit is set when the CR.RXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one.
This bit is set when the CR.TXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one.
This bit is set when a Receive Sync has occurred.
This bit is cleared when the SR register is read.
This bit is set when a Transmit Sync has occurred.
This bit is cleared when the SR register is read.
This bit is set when compare 1 has occurred.
This bit is cleared when the SR register is read.
This bit is set when compare 0 has occurred.
This bit is cleared when the SR register is read.
This bit is set when data has been loaded in the RHR register while previous data has not yet been read.
This bit is cleared when the SR register is read.
This bit is set when data has been received and loaded in the RHR register.
This bit is cleared when the RHR register is empty.
This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR
register has been transmitted.
This bit is cleared when data remains in the THR register or is currently transmitted from the TSR register.
Status Register
30
22
14
6
-
-
-
-
SR
Read-only
0x40
0x000000CC
OVRUN
29
21
13
5
-
-
-
RXRDY
28
20
12
4
-
-
-
RXSYN
27
19
11
3
-
-
-
TXSYN
26
18
10
2
-
-
-
TXEMPTY
RXEN
CP1
25
17
9
1
-
TXRDY
TXEN
CP0
24
16
8
0
-
540