AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 210

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.9.3
15.6.9.4
Figure 15-34. Access to Non-sequential Data within the Same Page
32072G–11/2011
A[AD_MSB:3]
A[2], A1, A0
CLK_SMC
D[7:0]
NRD
NCS
Page mode restriction
Sequential and non-sequential accesses
The page mode is not compatible with the use of the NWAIT signal. Using the page mode and
the NWAIT signal may lead to unpredictable behavior.
If the chip select and the MSB of addresses as defined in
then the current access lies in the same page as the previous one, and no page break occurs.
Using this information, all data within the same page, sequential or not sequential, are accessed
with a minimum access time (t
ory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long
access time (t
a short access time (t
If the MSB of addresses are different, the SMC performs the access of a new page. In the same
way, if the chip select is different from the previous access, a page break occurs. If two sequen-
tial accesses are made to the page mode memory, but separated by an other internal or external
peripheral access, a page break occurs on the second access because the chip select of the
device was deasserted between both accesses.
NCSRDPULSE
pa
). Accesses to D3 and D7, though they are not sequential accesses, only require
A1
sa
).
sa
).
D1
Figure 15-34 on page 210
Page address
NRDPULSE
A3
D3
Table 15-6 on page 208
illustrates access to an 8-bit mem-
NRDPULSE
A7
D7
are identical,
210