AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 330

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32072G–11/2011
Note:
Note:
3. Write the channel configuration information into the CFGx register for channel x.
4. Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the
5. Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the
6. Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory
7. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI
8. Clear any pending interrupts on the channel from the previous DMA transfer by writing
9. Program the CTLx, CFGx registers according to Row 10 as shown in
10. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
11. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit. The transfer is
12. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
13. Source and destination request single and burst DMA transactions to transfer the block
14. The DMACA does not wait for the block interrupt to be cleared, but continues fetching
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
a. Designate the handshaking interface type (hardware or software) for the source
b. If the hardware handshaking interface is activated for the source or destination
last) are set as shown in Row 10 of
the last Linked List Item must be set as described in Row 1 or Row 5 of
page
last) are non-zero and point to the base address of the next Linked List Item.
point to the start source/destination block address preceding that LLI fetch.
entries in memory are cleared.
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that
all interrupts have been cleared.
page
performed.
of data (assuming non-memory peripheral). The DMACA acknowledges at the comple-
tion of every transaction (burst and single) in the block and carry out the block transfer.
the next LLI from the memory location pointed to by current LLPx register and automat-
ically reprograms the SARx, DARx, LLPx and CTLx channel registers. The DMA
The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers are fetched. The DMACA automati-
cally reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0).
Table 19-1 on page 326
nation) and flow control device by programming the TT_FC of the CTLx register.
and destination peripherals. This is not required for memory. This step requires pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
peripheral, assign the handshaking interface to the source and destination periph-
eral. This requires programming the SRC_PER and DEST_PER bits, respectively.
326.
326.
Figure 19-9 on page 332
Table 19-1 on page
shows a Linked List example with two list items.
326. The LLI.CTLx register of
Table 19-1 on
Table 19-1 on
330