AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 498

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.9.8
Name:
Access Type:
Offset:
Reset Value:
• MENB: Master Interface Enable
• STOP: Stop Request Accepted
• PECERR: PEC Error
• TOUT: Timeout
• SMBALERT: SMBus Alert
• ARBLST: Arbitration Lost
• DNAK: NAK in Data Phase Received
• ANAK: NAK in Address Phase Received
• BUSFREE: Two-wire Bus is Free
32072G–11/2011
31
23
15
7
-
-
-
-
0: Master interface is disabled.
1: Master interface is enabled.
This bit is one when a STOP request caused by writing a one to CR.STOP has been accepted, and transfer has stopped.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when a SMBus PEC error occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when a SMBus timeout occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when an SMBus Alert was received.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority
transmission in progress by a different master.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when no ACK was received form slave during data transmission.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when no ACK was received from slave during address phase
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
This bit is one when activity has completed on the two-wire bus.
Otherwise, this bit is cleared.
Status Register
STOP
30
22
14
6
-
-
-
SR
Read-only
0x1C
0x00000002
BUSFREE
PECERR
29
21
13
5
-
-
TOUT
IDLE
28
20
12
4
-
-
SMBALERT
CCOMP
27
19
11
3
-
-
ARBLST
CRDY
26
18
10
2
-
-
TXRDY
DNAK
25
17
9
1
-
-
RXRDY
MENB
ANAK
24
16
8
0
-
498