AT32UC3A464 Atmel Corporation, AT32UC3A464 Datasheet - Page 182

• Manufacturer Part Number: AT32UC3A464
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A464

• Flash (kbytes): 64 Kbytes
• Pin Count: 100
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• Hardware Qtouch Acquisition: No
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Ssc: 1
• Sd / Emmc: 2
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 128
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.6.4
32072G–11/2011
Standard Read and Write Protocols
•Signal multiplexing
Figure 15-6.
Depending on the MODE.BAT bit, only the write signals or the byte select signals are used. To
save I/Os at the external bus interface, control signals at the SMC interface are multiplexed.
For 16-bit devices, bit A0 of address is unused. When byte select option is selected, NWR1 is
unused. When byte write option is selected, NBS0 to NBS1 are unused.
Table 15-3.
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to
NBS1) always have the same timing as the address bus (A). NWE represents either the NWE
signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write
Signal Name
Device Type
Byte Access Type (BAT)
NBS0_A0
NWE_NWR0
NBS1_NWR1
NBS2_NWR2_A1
SMC Multiplexed Signal Translation
Connection of two 8-bit Devices on a 16-bit Bus: Byte Write Option
SMC
Byte Select
D[15:8]
NCS[3]
A[24:2]
1 x 16-bit
D[7:0]
NWR0
NWR1
NRD
NBS0
NBS1
NWE
A1
A1
16-bit Bus
Byte Write
2 x 8-bit
NWR0
NWR1
A1
8-bit Bus
1 x 8-bit
A[23:1]
A[0]
Write Enable
Read Enable
Memory Enable
NWE
D[15:8]
A[23:1]
A[0]
Write Enable
Read Enable
Memory Enable
D[7:0]
A0
A1
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