AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 944
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A364-ALU
Manufacturer:
ATMEL
Quantity:
230
Company:
Part Number:
AT32UC3A364-ALUR
Manufacturer:
AVAGO
Quantity:
11 439
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 944 of 1012
- Download datasheet (16Mb)
32072G–11/2011
The size field is encoded as i
Table 34-18. Size Field Semantics
Starting in Run-Test/Idle, SAB data is accessed in the following way:
For any operation, the full 36 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 34-19. MEMORY_SIZED_ACCESS Details
Size field value
00
01
10
11
Instructions
IR input value
IR output value
DR Size
DR input value (Address phase)
DR input value (Data read phase)
DR input value (Data write phase)
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write), 2-bit access size, and the 36-bit
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a
9. Return to Run-Test/Idle.
address of the data to access.
write operation, scan in the new contents of the area.
Access size
Byte (8 bits)
Halfword (16 bits)
Word (32 bits)
Reserved
Table
34-18.
Details
10101 (0x15)
peb01
39 bits
aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx
dddddddd dddddddd dddddddd dddddddd xxxxxxx
Data alignment
Address modulo 4 : data alignment
0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx
1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx
2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx
3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd
Address modulo 4 : data alignment
0: dddddddd dddddddd xxxxxxxx xxxxxxxx
1: Not allowed
2: xxxxxxxx xxxxxxxx dddddddd dddddddd
3: Not allowed
Address modulo 4 : data alignment
0: dddddddd dddddddd dddddddd dddddddd
1: Not allowed
2: Not allowed
3: Not allowed
N/A
944
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