AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 700
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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ATMEL
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 700 of 1012
- Download datasheet (16Mb)
• FIFOCON: FIFO Control
• KILLBK: Kill IN Bank
• NBUSYBKE: Number of Busy Banks Interrupt Enable
• ERRORTRANSE: Transaction Error Interrupt Enable
• DATAXE: DataX Interrupt Enable
• MDATAE: MData Interrupt Enable
• SHORTPACKETE: Short Packet Interrupt Enable
• STALLEDE: STALLed Interrupt Enable
• CRCERRE: CRC Error Interrupt Enable
• OVERFE: Overflow Interrupt Enable
• NAKINE: NAKed IN Interrupt Enable
• HBISOFLUSHE: High Bandwidth Isochronous IN Flush Interrupt Enable
32072G–11/2011
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read,
their value is always 0.
For IN endpoints:
This bit is set when the current bank is free, at the same time as TXINI.
This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
For OUT endpoints:
This bit is set when the current bank is full, at the same time as RXOUTI.
This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank.
This bit is set when the KILLBKS bit is written to one. This will kill the last written bank.
This bit is cleared by hardware after the completion of the “kill packet procedure”.
The user shall wait for this bit to be cleared before trying to process another IN packet.
Caution: The bank is cleared when the “kill packet” procedure is completed by the USBB core :
If the bank is really killed, the NBUSYBK field is decremented.
If the bank is not “killed” but sent (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case
can occur if at the same time an IN token is coming and the user wants to kill this bank.
Note : If two banks are ready to be sent, the above specific case can not occur, because the first bank is sent (IN transfer) while
the last bank is killed.
This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK).
This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt
(NBUSYBK).
This bit is set when the ERRORTRANSES bit is written to one. This will enable the transaction error interrupt (ERRORTRANS).
This bit is cleared when the ERRORTRANSEC bit is written to one. This will disable the transaction error interrupt
(ERRORTRANS).
This bit is set when the DATAXES bit is written to one. This will enable the DATAX interrupt. (see DTSEQ bits)
This bit is cleared when the DATAXEC bit is written to one. This will disable the DATAX interrupt.
This bit is set when the MDATAES bit is written to one. This will enable the Multiple DATA interrupt. (see DTSEQ bits)
This bit is cleared when the MDATAEC bit is written to one. This will disable the Multiple DATA interrupt.
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt
(SHORTPACKET).
This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI).
This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI).
This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI).
This bit is cleared when the CRCERREC bit is written to one. This will disable the CRC Error interrupt (CRCERRI).
This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI).
This bit is cleared when the OVERFEC bit is written to one. This will disable the Overflow interrupt (OVERFI).
This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI).
This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI).
This bit is set when the HBISOFLUSHES bit is written to one. This will enable the HBISOFLUSHI interrupt.
700
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