AT32UC3A364 Atmel Corporation, AT32UC3A364 Datasheet - Page 478
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AT32UC3A364
Manufacturer Part Number
AT32UC3A364
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A364
Flash (kbytes)
64 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A364-ALU
Manufacturer:
ATMEL
Quantity:
230
Company:
Part Number:
AT32UC3A364-ALUR
Manufacturer:
AVAGO
Quantity:
11 439
Part Number:
AT32UC3A364S-ALUT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 478 of 1012
- Download datasheet (16Mb)
23.8.2.1
32072G–11/2011
Clock Generation
The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK
clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR
describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be
selected through the Clock Prescaler field in CWGR (CWGR.EXP).
CWGR has the following fields:
LOW: Prescaled clock cycles in clock low count. Used to time T
HIGH: Prescaled clock cycles in clock high count. Used to time T
STASTO: Prescaled clock cycles in clock high count. Used to time T
DATA: Prescaled clock cycles for data setup and hold count. Used to time T
EXP: Specifies the clock prescaler setting.
Note that the total clock low time generated is the sum of T
Any slave or other bus master taking part in the transfer may extend the TWCK low period at any
time.
The TWIM hardware monitors the state of the TWCK line as required by the I²C specification.
The clock generation counters are started when a high/low level is detected on the TWCK line,
not when the TWIM hardware releases/drives the TWCK line. This means that the CWGR set-
tings alone do not determine the TWCK frequency. The CWGR settings determine the clock low
time and the clock high time, but the TWCK rise and fall times are determined by the external cir-
cuitry (capacitive load, etc.).
Figure 23-5. Bus Timing Diagram
S
t
t LOW
HD:STA
t
SU:DAT
t HIGH
t
HD:DAT
f
PRESCALER
t LOW
=
f
------------------------- -
2
CLK_TWIM
(
t
t
EXP
SU:DAT
SU:STA
+
1
)
HD_DAT
Sr
LOW
HIGH
+ T
and T
HD_STA
.
SU_DAT
BUF
, T
HD_DAT
+ T
.
t
SU_STA
SU:STO
LOW
, T
.
, T
SU_DAT
SU_STO
P
.
478
.
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